| SpiNNaker 2: A 10 million core processor system for brain simulation and machine learning-Keynote presentation C Mayr, S Hoeppner, S Furber Communicating Process Architectures 2017 & 2018, 277-280, 2019 | 133 | 2019 |
| A biological-realtime neuromorphic system in 28 nm CMOS using low-leakage switched capacitor circuits C Mayr, J Partzsch, M Noack, S Hänzsche, S Scholze, S Höppner, ... IEEE transactions on biomedical circuits and systems 10 (1), 243-254, 2015 | 109 | 2015 |
| Memory-efficient deep learning on a SpiNNaker 2 prototype C Liu, G Bellec, B Vogginger, D Kappel, J Partzsch, F Neumärker, ... Frontiers in neuroscience 12, 840, 2018 | 65 | 2018 |
| 10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS B Noethen, O Arnold, EP Adeva, T Seifert, E Fischer, S Kunze, E Matúš, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 56 | 2014 |
| A fast-locking ADPLL with instantaneous restart capability in 28-nm CMOS technology S Höppner, S Haenzsche, G Ellguth, D Walter, H Eisenreich, R Schüffny IEEE Transactions on Circuits and Systems II: Express Briefs 60 (11), 741-745, 2013 | 55 | 2013 |
| A 32 GBit/s communication SoC for a waferscale neuromorphic system S Scholze, H Eisenreich, S Höppner, G Ellguth, S Henker, M Ander, ... Integration 45 (1), 61-75, 2012 | 53 | 2012 |
| A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS D Walter, S Höppner, H Eisenreich, G Ellguth, S Henker, S Hänzsche, ... 2012 IEEE International Solid-State Circuits Conference, 180-182, 2012 | 52 | 2012 |
| VLSI implementation of a 2.8 Gevent/s packet-based AER interface with routing and event sorting functionality S Scholze, S Schiefer, J Partzsch, S Hartmann, CG Mayr, S Höppner, ... Frontiers in neuroscience 5, 117, 2011 | 49 | 2011 |
| The SpiNNaker 2 processing element architecture for hybrid digital neuromorphic computing S Höppner, Y Yan, A Dixius, S Scholze, J Partzsch, M Stolba, F Kelber, ... arXiv preprint arXiv:2103.08392, 2021 | 48 | 2021 |
| Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS M Noack, J Partzsch, CG Mayr, S Hänzsche, S Scholze, S Höppner, ... Frontiers in neuroscience 9, 10, 2015 | 47 | 2015 |
| Efficient reward-based structural plasticity on a SpiNNaker 2 prototype Y Yan, D Kappel, F Neumärker, J Partzsch, B Vogginger, S Höppner, ... IEEE transactions on biomedical circuits and systems 13 (3), 579-591, 2019 | 46 | 2019 |
| A fixed point exponential function accelerator for a neuromorphic many-core system J Partzsch, S Höppner, M Eberlein, R Schüffny, C Mayr, DR Lester, ... 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 46 | 2017 |
| Comparing Loihi with a SpiNNaker 2 prototype on low-latency keyword spotting and adaptive robotic control Y Yan, TC Stewart, X Choo, B Vogginger, J Partzsch, S Höppner, F Kelber, ... Neuromorphic Computing and Engineering 1 (1), 014002, 2021 | 41 | 2021 |
| A heterogeneous SDR MPSoC in 28 nm CMOS for low-latency wireless applications S Haas, T Seifert, B Nöthen, S Scholze, S Höppner, A Dixius, EP Adeva, ... Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 39 | 2017 |
| A compact clock generator for heterogeneous GALS MPSoCs in 65-nm CMOS technology S Hoppner, H Eisenreich, S Henker, D Walter, G Ellguth, R Schuffny IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (3), 566-570, 2012 | 36 | 2012 |
| A power management architecture for fast per-core DVFS in heterogeneous MPSoCs S Höppner, C Shao, H Eisenreich, G Ellguth, M Ander, R Schüffny 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 261-264, 2012 | 35 | 2012 |
| Dynamic voltage and frequency scaling for neuromorphic many-core systems S Höppner, Y Yan, B Vogginger, A Dixius, J Partzsch, F Neumärker, ... 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 30 | 2017 |
| Adaptive body bias aware implementation for ultra-low-voltage designs in 22FDX technology S Höppner, H Eisenreich, D Walter, A Scharfe, A Oefelein, F Schraut, ... IEEE Transactions on Circuits and Systems II: Express Briefs 67 (10), 2159-2163, 2019 | 29 | 2019 |
| Reducing the computational footprint for real-time BCPNN learning B Vogginger, R Schüffny, A Lansner, L Cederström, J Partzsch, ... Frontiers in neuroscience 9, 2, 2015 | 29 | 2015 |
| A 335Mb/s 3.9mm265nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates M Winter, S Kunze, EP Adeva, B Mennenga, E Matûs, G Fettweis, ... 2012 IEEE International Solid-State Circuits Conference, 216-218, 2012 | 29 | 2012 |
Christian MayrProfessor, Technische Universität Dresden在 tu-dresden.de 的电子邮件经过验证
