| A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging K Mistry, C Allen, C Auth, B Beattie, D Bergstrom, M Bost, M Brazier, ... 2007 IEEE International Electron Devices Meeting, 247-250, 2007 | 1695 | 2007 |
| A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors C Auth, C Allen, A Blattner, D Bergstrom, M Brazier, M Bost, M Buehler, ... 2012 symposium on VLSI technology (VLSIT), 131-132, 2012 | 1044 | 2012 |
| A 90-nm logic technology featuring strained-silicon SE Thompson, M Armstrong, C Auth, M Alavi, M Buehler, R Chau, S Cea, ... IEEE Transactions on electron devices 51 (11), 1790-1797, 2004 | 947 | 2004 |
| A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate … C Auth, A Aliyarukunju, M Asoro, D Bergstrom, V Bhagwat, J Birdsall, ... 2017 IEEE International Electron Devices Meeting (IEDM), 29.1. 1-29.1. 4, 2017 | 460 | 2017 |
| A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1/spl mu/m/sup 2/SRAM cell S Thompson, N Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, ... Digest. International Electron Devices Meeting,, 61-64, 2002 | 456 | 2002 |
| A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product … CH Jan, M Agostinelli, M Buehler, ZP Chen, SJ Choi, G Curello, ... 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 368 | 2009 |
| IEEE International Electron Devices Meeting (IEDM) CH Jan, M Agostinelli, M Buehler, ZP Chen, SJ Choi, G Curello, ... San Francisco, USA, 3.1, 2012 | 341 | 2012 |
| The double‐ring electrodynamic balance for microparticle characterization EJ Davis, MF Buehler, TL Ward Review of Scientific Instruments 61 (4), 1281-1288, 1990 | 168 | 1990 |
| IEDM Tech. Dig. S Thompson, N Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, ... IEDM Tech. Dig, 61, 2002 | 99 | 2002 |
| 90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology CH Jan, J Bielefeld, M Buehler, V Chikamane, K Fischer, T Hepburn, ... Proceedings of the IEEE 2003 International Interconnect Technology …, 2003 | 79 | 2003 |
| Microparticle Raman spectroscopy of multicomponent aerosols MF Buehler, TM Allen, EJ Davis Journal of colloid and interface science 146 (1), 79-89, 1991 | 67 | 1991 |
| Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing D Ingerly, A Agrawal, R Ascazubi, A Blattner, M Buehler, V Chikarmane, ... 2012 IEEE International Interconnect Technology Conference, 1-3, 2012 | 59 | 2012 |
| A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors CH Jan, P Bai, S Biswas, M Buehler, ZP Chen, G Curello, S Gannavaram, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 56 | 2008 |
| Nanophase iron-based liquefaction catalysts: Synthesis, characterization, and model compound reactivity DW Matson, JC Linehan, JG Darab, MF Buehler Energy & Fuels 8 (1), 10-18, 1994 | 54 | 1994 |
| Radiometric effects on absorbing microspheres TM Allen, MF Buehler, EJ Davis Journal of colloid and interface science 142 (2), 343-356, 1991 | 50 | 1991 |
| Low-k interconnect stack with a novel self-aligned via patterning process for 32nm high volume manufacturing R Brain, S Agrawal, D Becher, R Bigwood, M Buehler, V Chikarmane, ... 2009 IEEE International Interconnect Technology Conference, 249-251, 2009 | 47 | 2009 |
| Interconnect stack using self-aligned quad and double patterning for 10nm high volume manufacturing A Yeoh, A Madhavan, N Kybert, S Anand, J Shin, M Asoro, ... 2018 IEEE International Interconnect Technology Conference (IITC), 144-147, 2018 | 34 | 2018 |
| Intel 4 CMOS technology featuring advanced FinFET transistors optimized for high density and high-performance computing B Sell, S An, J Armstrong, D Bahr, B Bains, R Bambery, K Bang, D Basu, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 28 | 2022 |
| Facilitating removal of sacrificial layers to form replacement metal gates J Kavalieros, J Brask, M Doczy, C Barns, M Metz, S Datta, R Chau, ... US Patent App. 10/925,458, 2006 | 22 | 2006 |
| Separation of monovalent cations by electrodialysis JD NORTON, MF BUEHLER Separation science and technology 29 (12), 1553-1566, 1994 | 19 | 1994 |
