| Leakage reduction of SRAM-based look-up table using dynamic power gating A Nag, D Nath, SN Pradhan Journal of Circuits, Systems and Computers 26 (03), 1750041, 2017 | 11 | 2017 |
| FPGA and ASIC realisation of EMD algorithm for real‐time signal processing K Das, D Nath, SN Pradhan IET Circuits, Devices & Systems 14 (6), 741-749, 2020 | 8 | 2020 |
| CG-in-PG architecture implementation for power reduction in FSMs P Choudhury, A Nag, D Nath, SN Pradhan International Journal of Electronics Letters 2 (3), 180-185, 2014 | 3 | 2014 |
| Power gating architecture implementation inside clock period to reduce power D Nath, P Choudhury, A Nag, SN Pradhan International Journal of Computer Aided Engineering and Technology 5 6 (3 …, 2014 | 3 | 2014 |
| Hybrid approach of within-clock power gating and normal power gating to reduce power D Nath, P Choudhury, SN Pradhan Journal of Circuits, Systems and Computers 25 (05), 1650044, 2016 | 2 | 2016 |
| Thermal aware AND-OR-XOR network synthesis P Choudhury, D Nath, V Rai, SN Pradhan 2015 19th International Symposium on VLSI Design and Test, 1-6, 2015 | 2 | 2015 |
| Power reduction by integrated within_clock_power gating and power gating (WCPG_in_PG) D Nath, P Choudhury, SN Pradhan VLSI Design and Test: 17th International Symposium, VDAT 2013, Jaipur, India …, 2013 | 1 | 2013 |
| Within-clock power gating architecture implimentation to reduce leakage SN Pradhan, D Nath, P Choudhury, A Nag 2012 5th International Conference on Computers and Devices for Communication …, 2012 | 1 | 2012 |
| Printed Circuit Board Design of a Low Power, Lightweight and Compact 3D Structured Air Quality Monitoring System KD Purkayastha, D Nath, VK Singh, SN Pradhan | | 2021 |
| Low Dropout Based Noise Minimization of Active Mode Power Gated Circuit D Nath, SN Pradhan International Journal of Engineering 31 (9), 1546-1552, 2018 | | 2018 |
| Transistor level realisation of power gated FSM SN Pradhan, P Choudhury, D Nath International Journal of Computer Aided Engineering and Technology 9 (3 …, 2017 | | 2017 |
| Design of new high-speed and low-energy dynamic PLA SN Pradhan, S Bhowmik, P Choudhury, D Nath, A Nag, D Deb, B Paul International Journal of Electronics Letters 4 (1), 87-92, 2016 | | 2016 |
| Layout-oriented look up table-based dual threshold approach to reduce leakage SN Pradhan, A Chakraborty, A Nag, D Nath International Journal of Computer Aided Engineering and Technology 7 (4 …, 2015 | | 2015 |
