| Monolithic optical microlithography of high-density elastic circuits YQ Zheng, Y Liu, D Zhong, S Nikzad, S Liu, Z Yu, D Liu, HC Wu, C Zhu, ... Science 373 (6550), 88-94, 2021 | 219 | 2021 |
| Bio-inspired neurons based on novel leaky-FeFET with ultra-low hardware cost and advanced functionality for all-ferroelectric neural network C Chen, M Yang, S Liu, T Liu, K Zhu, Y Zhao, H Wang, Q Huang, R Huang 2019 Symposium on VLSI Technology, T136-T137, 2019 | 57 | 2019 |
| Capacitor-less stochastic leaky-FeFET neuron of both excitatory and inhibitory connections for SNN with reduced hardware cost J Luo, L Yu, T Liu, M Yang, Z Fu, Z Liang, L Chen, C Chen, S Liu, S Wu, ... 2019 IEEE International Electron Devices Meeting (IEDM), 6.4. 1-6.4. 4, 2019 | 54 | 2019 |
| A novel negative capacitance tunnel FET with improved subthreshold swing and nearly non-hysteresis through hybrid modulation Y Zhao, Z Liang, Q Huang, C Chen, M Yang, Z Sun, K Zhu, H Wang, S Liu, ... IEEE electron device letters 40 (6), 989-992, 2019 | 32 | 2019 |
| High-speed and large-scale intrinsically stretchable integrated circuits D Zhong, C Wu, Y Jiang, Y Yuan, M Kim, Y Nishio, CC Shih, W Wang, ... Nature 627 (8003), 313-320, 2024 | 26 | 2024 |
| The future of hardware technologies for computing: N3XT 3D MOSAIC, illusion scaleup, co-design RM Radway, K Sethi, WC Chen, J Kwon, S Liu, TF Wu, E Beigne, ... 2021 IEEE International Electron Devices Meeting (IEDM), 25.4. 1-25.4. 4, 2021 | 15 | 2021 |
| Co-designed Capacitive Coupling-Immune Sensing Scheme for Indium-Tin-Oxide (ITO) 2T Gain Cell Operating at Positive Voltage Below 2 V K Toprasertpong, S Liu, J Chen, S Wahid, K Jana, WC Chen, S Li, E Pop, ... 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 6 | 2023 |
| Gain Cell Memory on Logic Platform–Device Guidelines for Oxide Semiconductor Transistor Materials Development S Liu, K Jana, K Toprasertpong, J Chen, Z Liang, Q Jiang, S Wahid, S Qin, ... 2023 International Electron Devices Meeting (IEDM), 1-4, 2023 | 4 | 2023 |
| 8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory S Qin, M Tung, E Belliveau, S Liu, J Kwon, WC Chen, Z Jiang, SS Wong, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 4 | 2022 |
| Design Guidelines for Oxide Semiconductor Gain Cell Memory on a Logic Platform S Liu, K Jana, K Toprasertpong, J Chen, Z Liang, Q Jiang, S Wahid, S Qin, ... IEEE Transactions on Electron Devices, 2024 | | 2024 |
| Hybrid 2T nMOS/pMOS Gain Cell Memory with Indium-tin-oxide and Carbon Nanotube MOSFETs for Counteracting Capacitive Coupling S Liu, S Li, Q Lin, K Jana, S Mitra, HSP Wong, K Toprasertpong IEEE Electron Device Letters, 2023 | | 2023 |
| Implementation of Lateral Divisive Inhibition Based on Ferroelectric Fet with Ultra-Low Hardware Cost for Neuromorphic Computing S Liu, T Liu, Z Fu, C Chen, Q Huang, R Huang 2020 China Semiconductor Technology International Conference (CSTIC), 1-3, 2020 | | 2020 |
H.-S. Philip WongProfessor of Electrical Engineering, Stanford University在 stanford.edu 的电子邮件经过验证
H.-S. Philip WongProfessor of Electrical Engineering, Stanford University在 stanford.edu 的电子邮件经过验证