| DRAMSim2: A cycle accurate memory system simulator P Rosenfeld, E Cooper-Balis, B Jacob IEEE computer architecture letters 10 (1), 16-19, 2011 | 1165 | 2011 |
| The structural simulation toolkit AF Rodrigues, KS Hemmert, BW Barrett, C Kersey, R Oldfield, M Weston, ... ACM SIGMETRICS Performance Evaluation Review 38 (4), 37-42, 2011 | 428 | 2011 |
| Fine-grained activation for power reduction in DRAM E Cooper-Balis, B Jacob IEEE Micro 30 (3), 34-47, 2010 | 91 | 2010 |
| Buffer-on-board memory systems E Cooper-Balis, P Rosenfeld, B Jacob ACM SIGARCH Computer Architecture News 40 (3), 392-403, 2012 | 70 | 2012 |
| Improvements to the structural simulation toolkit A Rodrigues, K Bergman, D Bunde, E Cooper-Balis, K Ferreira, ... Fifth International Conference on Simulation Tools and Techniques, 2012 | 30 | 2012 |
| Parallel network motif finding M Schatz, E Cooper-Balis, A Bazinet Techinical report, University of Maryland Insitute for Advanced Computer Studies, 2008 | 24 | 2008 |
| Peering over the memory wall: Design space and performance analysis of the hybrid memory cube P Rosenfeld, E Cooper-Balis, T Farrell, D Resnick, B Jacob Univ. of Maryland Systems and Computer Architecture Group, Tech. Rep. UMD …, 2012 | 21 | 2012 |
| Microhotplate temperature sensor calibration and BIST M Afridi, C Montgomery, E Cooper-Balis, S Semancik, KG Kreider, J Geist Journal of Research of the National Institute of Standards and Technology …, 2011 | 15 | 2011 |
| Analog BIST functionality for microhotplate temperature sensors M Afridi, CB Montgomery, E Cooper-Balis, S Semancik, KG Kreider, ... IEEE Electron Device Letters 30 (9), 928-930, 2009 | 11 | 2009 |
| DRAMSim2 P Rosenfeld, E Cooper-Balis, B Jacob | 7 | 2010 |
| Translation system for finer grain memory architectures B Keeth, RC Murphy, EC Cooper-Balis US Patent 11,281,608, 2022 | 6 | 2022 |
| Cache memory addressing JT Pawlowski, EC Cooper-Balis, DA Roberts US Patent 11,436,144, 2022 | 5 | 2022 |
| Translation system for finer grain memory architectures B Keeth, RC Murphy, EC Cooper-Balis US Patent 10,838,897, 2020 | 3 | 2020 |
| Translation system for finer grain memory architectures B Keeth, RC Murphy, EC Cooper-Balis US Patent 10,628,354, 2020 | 3 | 2020 |
| Access tracking in memory C Dirik, RM Walker, EC Cooper-Balis US Patent 11,893,279, 2024 | 2 | 2024 |
| Translation system for finer grain memory architectures B Keeth, RC Murphy, EC Cooper-Balis US Patent 11,755,515, 2023 | 1 | 2023 |
| Area-optimized row hammer mitigation S Ayyapureddi, Y Lu, E Gieske, C Dirik, AD Akel, EC Cooper-Balis, ... US Patent App. 17/897,813, 2023 | 1 | 2023 |
| Aliased row hammer detector E Gieske, C Dirik, RM Walker, S Ayyapureddi, N Izzo, M Geiger, Y Lu, ... US Patent App. 17/941,655, 2023 | 1 | 2023 |
| Multiple memory type shared memory bus systems and methods DA Roberts, JT Pawlowski, E Cooper-Balis US Patent 11,281,604, 2022 | 1 | 2022 |
| MEMORY DEVICE SECURITY AND ROW HAMMER MITIGATION Y Lu, S Ayyapureddi, EJ Gieske, C Dirik, AD Akel, EC Cooper-balis, ... US Patent App. 18/808,887, 2024 | | 2024 |
