| A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18m CMOS SK Lee, YH Seo, HJ Park, JY Sim IEEE Journal of Solid-State Circuits 45 (12), 2874-2881, 2010 | 211 | 2010 |
| A 21 fJ/conversion-step 100 kS/s 10-bit ADC with a low-noise time-domain comparator for low-power sensor interface SK Lee, SJ Park, HJ Park, JY Sim IEEE Journal of Solid-State Circuits 46 (3), 651-659, 2011 | 207 | 2011 |
| Empirical equations on electrical parameters of coupled microstrip lines for crosstalk estimation in printed circuit board YS Sohn, JC Lee, HJ Park, SI Cho IEEE Transactions on advanced packaging 24 (4), 521-527, 2001 | 136 | 2001 |
| A digital-domain calibration of split-capacitor DAC for a differential SAR ADC without additional analog circuits JY Um, YJ Kim, EW Song, JY Sim, HJ Park IEEE Transactions on Circuits and Systems I: Regular Papers 60 (11), 2845-2856, 2013 | 134 | 2013 |
| 5.8 A 9.3 nW all-in-one bandgap voltage and current reference circuit Y Ji, C Jeon, H Son, B Kim, HJ Park, JY Sim 2017 IEEE International Solid-State Circuits Conference (ISSCC), 100-101, 2017 | 115 | 2017 |
| A 1.25 ps Resolution 8b Cyclic TDC in 0.13m CMOS YH Seo, JS Kim, HJ Park, JY Sim IEEE Journal of Solid-State Circuits 47 (3), 736-743, 2011 | 112 | 2011 |
| A serpentine guard trace to reduce the far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines K Lee, HB Lee, HK Jung, JY Sim, HJ Park IEEE transactions on advanced packaging 31 (4), 809-817, 2008 | 108 | 2008 |
| A charge sheet capacitance model of short channel MOSFETs for SPICE HJ Park, PK Ko, C Hu IEEE transactions on computer-aided design of integrated circuits and …, 1991 | 108 | 1991 |
| 5.7 A 29nW bandgap reference circuit JM Lee, Y Ji, S Choi, YC Cho, SJ Jang, JS Choi, B Kim, HJ Park, JY Sim 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 100 | 2015 |
| Memory system having multi-terminated multi-drop bus HJ Park, SJ Bae US Patent 7,274,583, 2007 | 99 | 2007 |
| A 300-MS/s, 1.76-ps-resolution, 10-b asynchronous pipelined time-to-digital converter with on-chip digital background calibration in 0.13-µm CMOS JS Kim, YH Seo, Y Suh, HJ Park, JY Sim IEEE Journal of Solid-State Circuits 48 (2), 516-526, 2012 | 81 | 2012 |
| A 1.3 μW 0.6 V 8.7-ENOB successive approximation ADC in a 0.18 μm CMOS SK Lee, SJ Park, Y Suh, HJ Park, JY Sim 2009 Symposium on VLSI Circuits, 242-243, 2009 | 74 | 2009 |
| A 192-pW Voltage Reference Generating Bandgap– With Process and Temperature Dependence Compensation Y Ji, J Lee, B Kim, HJ Park, JY Sim IEEE Journal of Solid-State Circuits 54 (12), 3281-3291, 2019 | 73 | 2019 |
| A 0.63 ps resolution, 11b pipeline TDC in 0.13 µm CMOS YH Seo, JS Kim, HJ Park, JY Sim 2011 symposium on VLSI circuits-digest of technical papers, 152-153, 2011 | 71 | 2011 |
| Current mode differential transmission method and system for transmitting three units of data using four signal lines SW Choi, HJ Park US Patent 7,508,881, 2009 | 66 | 2009 |
| Serpentine microstrip lines with zero far-end crosstalk for parallel high-speed DRAM interfaces K Lee, HK Jung, HJ Chi, HJ Kwon, JY Sim, HJ Park IEEE Transactions on Advanced Packaging 33 (2), 552-558, 2009 | 65 | 2009 |
| A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate SK Lee, YS Kim, H Ha, Y Seo, HJ Park, JY Sim 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 63 | 2009 |
| An interpolating digitally controlled oscillator for a wide-range all-digital PLL KH Choi, JB Shin, JY Sim, HJ Park IEEE Transactions on Circuits and Systems I: Regular Papers 56 (9), 2055-2063, 2008 | 60 | 2008 |
| FEXT-eliminated stub-alternated microstrip line for multi-gigabit/second parallel links SK Lee, K Lee, HJ Park, JY Sim Electronics letters 44 (4), 272-273, 2008 | 60 | 2008 |
| CMOS digital duty cycle correction circuit for multi-phase clock YC Jang, SJ Bae, HJ Park Electronics Letters 39 (19), 1383-1384, 2003 | 56 | 2003 |
