| InP-based transistor fabrication P Ye, Z Cheng, Y Xuan, Y Wu, B Adekore, J Fiorenza US Patent 8,329,541, 2012 | 518 | 2012 |
| Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication AJ Lochtefeld, MT Currie, Z Cheng, J Fiorenza, G Braithwaite, TA Langdo US Patent 8,324,660, 2012 | 332* | 2012 |
| Semiconductor sensor structures with reduced dislocation defect densities Z Cheng, JG Fiorenza, C Sheen, A Lochtefeld US Patent 8,253,211, 2012 | 169* | 2012 |
| Solutions for integrated circuit integration of alternative active area materials AJ Lochtefeld, MT Currie, ZY Cheng, J Fiorenza US Patent 7,626,246, 2009 | 154 | 2009 |
| Aspect ratio trapping for mixed signal applications A Lochtefeld, J Fiorenza US Patent App. 11/857,047, 2008 | 139 | 2008 |
| Multi-junction solar cells J Fiorenza, AJ Lochtefeld US Patent 8,344,242, 2013 | 120 | 2013 |
| Fabrication and structures of crystalline material JS Park, JG Fiorenza US Patent App. 12/562,206, 2010 | 110 | 2010 |
| Polishing of small composite semiconductor materials JM Hydrick, JG Fiorenza US Patent 8,981,427, 2015 | 97 | 2015 |
| Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication AJ Lochtefeld, MT Currie, Z Cheng, J Fiorenza, G Braithwaite, TA Langdo US Patent 8,629,477, 2014 | 97 | 2014 |
| Film thickness constraints for manufacturable strained silicon CMOS JG Fiorenza, G Braithwaite, CW Leitz, MT Currie, J Yap, F Singaporewala, ... Semiconductor science and technology 19 (1), L4, 2003 | 97 | 2003 |
| Aspect ratio trapping: a unique technology for integrating Ge and III-Vs with silicon CMOS JG Fiorenza, JS Park, J Hydrick, J Li, J Li, M Curtin, M Carroll, ... ECS Transactions 33 (6), 963, 2010 | 93 | 2010 |
| Formation of devices by epitaxial layer overgrowth J Fiorenza, A Lochtefeld, J Bai, JS Park, J Hydrick, J Li, Z Cheng US Patent 8,034,697, 2011 | 81 | 2011 |
| Strained Si on insulator technology: from materials to devices TA Langdo, MT Currie, ZY Cheng, JG Fiorenza, M Erdtmann, ... Solid-State Electronics 48 (8), 1357-1367, 2004 | 80 | 2004 |
| Experimental comparison of RF power LDMOSFETs on thin-film SOI and bulk silicon JG Fiorenza, JA Del Alamo IEEE Transactions on Electron devices 49 (4), 687-692, 2002 | 65 | 2002 |
| Atomic-layer-deposited Al2O3/GaAs metal-oxide-semiconductor field-effect transistor on Si substrate using aspect ratio trapping technique YQ Wu, M Xu, PD Ye, Z Cheng, J Li, JS Park, J Hydrick, J Bai, M Carroll, ... Applied Physics Letters 93 (24), 2008 | 63 | 2008 |
| Fully depleted n-MOSFETs on supercritical thickness strained SOI I Lauer, TA Langdo, ZY Cheng, JG Fiorenza, G Braithwaite, MT Currie, ... IEEE Electron Device Letters 25 (2), 83-85, 2004 | 62 | 2004 |
| Low-defect-density Ge epitaxy on Si (001) using aspect ratio trapping and epitaxial lateral overgrowth JS Park, M Curtin, JM Hydrick, J Bai, JT Li, Z Cheng, M Carroll, ... Electrochemical and Solid-State Letters 12 (4), H142, 2009 | 59 | 2009 |
| RF power LDMOSFET on SOI JG Fiorenza, DA Antoniadis, JA del Alamo IEEE Electron device letters 22 (3), 139-141, 2001 | 59 | 2001 |
| Formation of devices by epitaxial layer overgrowth Z Cheng, J Fiorenza, JM Hydrick, AJ Lochtefeld, JS Park, J Bai, J Li US Patent 8,384,196, 2013 | 48* | 2013 |
| Thin film InP epitaxy on Si (001) using selective aspect ratio trapping J Li, J Bai, JM Hydrick, JG Fiorenza, C Major, M Carroll, Z Shellenbarger, ... ECS Transactions 18 (1), 887, 2009 | 40 | 2009 |
