| Challenges in building an open-source flow from RTL to bundled-data design Y Zhang, H Cheng, D Chen, H Fu, S Agarwal, M Lin, B Peter 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems …, 2018 | 11 | 2018 |
| SERAD: Soft error resilient asynchronous design using a bundled data protocol SA Aketi, S Gupta, H Cheng, J Mekie, PA Beerel IEEE Transactions on Circuits and Systems I: Regular Papers 67 (5), 1667-1677, 2020 | 9 | 2020 |
| Automatic retiming of two-phase latch-based resilient circuits H Cheng, HL Wang, M Zhang, D Hand, PA Beerel IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 6 | 2018 |
| Area optimization of timing resilient designs using resynthesis HH Huang, H Cheng, C Chu, PA Beerel IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 5 | 2017 |
| Test margin and yield in bundled data and ring-oscillator based designs Y Zhang, H Zha, V Sahir, H Cheng, PA Beerel 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems …, 2017 | 5 | 2017 |
| Area optimization of resilient designs guided by a mixed integer geometric program HH Huang, H Cheng, C Chu, PA Beerel Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 5 | 2016 |
| Converting flip-flop to clock-gated 3-phase latch-based designs using graph-based retiming H Cheng, X Li, Y Gu, PA Beerel IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 4 | 2021 |
| Saving power by converting flip-flop to 3-phase latch-based designs H Cheng, X Li, Y Gu, PA Beerel 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 574-579, 2020 | 2 | 2020 |
| Automatic conversion from flip-flop to 3-phase latch-based designs H Cheng, Y Gu, PA Beerel arXiv preprint arXiv:1906.10666, 2019 | 2 | 2019 |
| Yield modelling and analysis of bundled data and ring‐oscillator based designs Y Zhang, J Li, H Cheng, H Zha, J Draper, PA Beerel IET Computers & Digital Techniques 13 (3), 262-272, 2019 | 2 | 2019 |
| Two-phase asynchronous to synchronous interfaces for an open-source bundled-data flow A Abdelhadi, D Chen, H Cheng, G Datta, Y Zhang, P Beerel, ... 25th IEEE International Symposium on Asynchronous Circuits and Systems-Fresh …, 2019 | 1 | 2019 |
| RH-Blade: a radiation hardened asynchronous bundled-data design SA Aketi, S Gupta, H Cheng, J Mekie, P Beerel | 1 | 2018 |
| Deadline-aware joint optimization of sleep transistor and supply voltage for finfet based embedded systems H Cheng, J Li, J Draper, S Nazarian, Y Wang Proceedings of the Great Lakes Symposium on VLSI 2017, 427-430, 2017 | 1 | 2017 |
| SERAD: Soft Error Resilient Asynchronous Design using a Bundled Data Protocol S Aparna Aketi, S Gupta, H Cheng, J Mekie, PA Beerel arXiv e-prints, arXiv: 2001.04039, 2020 | | 2020 |
| A region based deep neural network for breast tumor differentiation in ultrasound elastography imaging HC Liu, H Cheng, YH Chou, CM Tiu, JX Wu, KK Shung American Institute of Ultrasound in Medicine (AIUM), 2019 | | 2019 |
| ASYNC 2018 A Moreno, J Cortadella, F Huemer, A Steininger, Y Zhang, H Cheng, ... | | |
Peter BeerelProfessor of Electrical and Computer Engineering, USC在 usc.edu 的电子邮件经过验证
