| PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors A Garofalo, M Rusci, F Conti, D Rossi, L Benini Philosophical Transactions of the Royal Society A 378 (2164), 20190155, 2020 | 147 | 2020 |
| Dory: Automatic end-to-end deployment of real-world dnns on low-cost iot mcus A Burrello, A Garofalo, N Bruschi, G Tagliavini, D Rossi, F Conti IEEE Transactions on Computers 70 (8), 1253-1268, 2021 | 108 | 2021 |
| A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference M Le Gallo, R Khaddam-Aljameh, M Stanisavljevic, A Vasilopoulos, ... Nature Electronics 6 (9), 680-693, 2023 | 75 | 2023 |
| XpulpNN: Accelerating quantized neural networks on RISC-V processors through ISA extensions A Garofalo, G Tagliavini, F Conti, D Rossi, L Benini 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 186-191, 2020 | 52 | 2020 |
| Pulp-nn: A computing library for quantized neural network inference at the edge on risc-v based parallel ultra low power clusters A Garofalo, M Rusci, F Conti, D Rossi, L Benini 2019 26th IEEE International Conference on Electronics, Circuits and Systems …, 2019 | 37 | 2019 |
| Xpulpnn: Enabling energy efficient and flexible inference of quantized neural networks on risc-v based iot end nodes A Garofalo, G Tagliavini, F Conti, L Benini, D Rossi IEEE Transactions on Emerging Topics in Computing 9 (3), 1489-1505, 2021 | 36 | 2021 |
| A mixed-precision RISC-V processor for extreme-edge DNN inference G Ottavi, A Garofalo, G Tagliavini, F Conti, L Benini, D Rossi 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 512-517, 2020 | 34 | 2020 |
| A heterogeneous in-memory computing cluster for flexible end-to-end inference of real-world deep neural networks A Garofalo, G Ottavi, F Conti, G Karunaratne, I Boybat, L Benini, D Rossi IEEE Journal on Emerging and Selected Topics in Circuits and Systems 12 (2 …, 2022 | 29 | 2022 |
| A low-power transprecision floating-point cluster for efficient near-sensor data analytics F Montagna, S Mach, S Benatti, A Garofalo, G Ottavi, L Benini, D Rossi, ... IEEE Transactions on Parallel and Distributed Systems 33 (5), 1038-1053, 2021 | 20 | 2021 |
| Enabling mixed-precision quantized neural networks in extreme-edge devices N Bruschi, A Garofalo, F Conti, G Tagliavini, D Rossi Proceedings of the 17th ACM International Conference on Computing Frontiers …, 2020 | 20 | 2020 |
| DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes: work-in-progress A Burrello, F Conti, A Garofalo, D Rossi, L Benini Proceedings of the International Conference on Hardware/Software Codesign …, 2019 | 20 | 2019 |
| A survey on deep learning hardware accelerators for heterogeneous hpc platforms C Silvano, D Ielmini, F Ferrandi, L Fiorin, S Curzel, L Benini, F Conti, ... arXiv preprint arXiv:2306.15552, 2023 | 16 | 2023 |
| A 1.15 TOPS/W, 16-cores parallel ultra-low power cluster with 2b-to-32b fully flexible bit-precision and vector lockstep execution mode A Garofalo, G Ottavi, A Di Mauro, F Conti, G Tagliavini, L Benini, D Rossi ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021 | 16 | 2021 |
| On-line testing for autonomous systems driven by risc-v processor design verification A Ruospo, R Cantoro, E Sanchez, PD Schiavone, A Garofalo, L Benini 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2019 | 16 | 2019 |
| 22.1 A 12.4 TOPS/W@ 136GOPS AI-IoT system-on-chip with 16 RISC-V, 2-to-8b precision-scalable DNN acceleration and 30%-boost adaptive body biasing F Conti, D Rossi, G Paulin, A Garofalo, A Di Mauro, G Rutishauer, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 21-23, 2023 | 13 | 2023 |
| Darkside: A heterogeneous risc-v compute cluster for extreme-edge on-chip dnn inference and training A Garofalo, Y Tortorella, M Perotti, L Valente, A Nadalini, L Benini, ... IEEE Open Journal of the Solid-State Circuits Society 2, 231-243, 2022 | 12 | 2022 |
| Dustin: A 16-cores parallel ultra-low-power cluster with 2b-to-32b fully flexible bit-precision and vector Lockstep execution mode G Ottavi, A Garofalo, G Tagliavini, F Conti, A Di Mauro, L Benini, D Rossi IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | 11 | 2023 |
| Xpulpnn: accelerating quantized neural networks on risc-v processors through isa extensions. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) A Garofalo, G Tagliavini, F Conti, D Rossi, L Benini IEEE, 2020 | 8 | 2020 |
| Wavelet-based Lamb waves direction of arrival estimation in passive monitoring techniques A Garofalo, N Testoni, A Marzani, L De Marchi 2016 IEEE International Ultrasonics Symposium (IUS), 1-4, 2016 | 8 | 2016 |
| Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing F Conti, G Paulin, A Garofalo, D Rossi, A Di Mauro, G Rutishauser, ... IEEE Journal of Solid-State Circuits, 2023 | 7 | 2023 |
Luca BeniniETH Zürich, Università di Bologna在 unibo.it 的电子邮件经过验证
