A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration M El-Chammas, B Murmann IEEE journal of solid-state circuits 46 (4), 838-847, 2011 | 410 | 2011 |
General analysis on the impact of phase-skew in time-interleaved ADCs M El-Chammas, B Murmann IEEE Transactions on Circuits and Systems I: Regular Papers 56 (5), 902-910, 2009 | 136 | 2009 |
A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC R Payne, C Sestok, W Bright, M El-Chammas, M Corsi, D Smith, N Tal 2011 IEEE International Solid-State Circuits Conference, 182-184, 2011 | 52 | 2011 |
Background calibration of time-interleaved data converters M El-Chammas, B Murmann Springer Science & Business Media, 2011 | 45 | 2011 |
A 12 bit 1.6 GS/s BiCMOS 2× 2 hierarchical time-interleaved pipeline ADC M El-Chammas, X Li, S Kimura, K Maclean, J Hu, M Weaver, ... IEEE Journal of Solid-State Circuits 49 (9), 1876-1885, 2014 | 41 | 2014 |
15.8 90dB-SFDR 14b 500MS/S BiCMOS switched-current pipelined ADC M El-Chammas, X Li, S Kimura, J Coulon, J Hu, D Smith, P Landman, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 32 | 2015 |
Background calibration of timing skew in time-interleaved A/D converters M El-Chammas Stanford University, 2010 | 22 | 2010 |
Background DAC calibration for pipeline ADC MI El-Chammas US Patent 9,136,856, 2015 | 16 | 2015 |
Voltage domain correction technique for timing skew errors in time interleaved ADCs PK Venkatachala, A ElShater, Y Xu, M El-Chammas, UK Moon 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 7 | 2017 |
Robust encoder for folding analog to digital converter MI El-Chammas US Patent 8,547,269, 2013 | 4 | 2013 |
Time-Interleaved ADCs M El-Chammas, B Murmann, M El-Chammas, B Murmann Background calibration of time-interleaved data converters, 5-30, 2012 | 4 | 2012 |
Implementing Security in RFID systems-the” Tag Emulator” M El-Chammas, B El-Khoury, A Halaby 3rd FEA Student Conference, 2004 | 4 | 2004 |
Analog to digital converter error rate reduction MI El-Chammas US Patent 9,941,896, 2018 | 3 | 2018 |
Track and hold with active charge cancellation H Aggrawal, MI El-Chammas US Patent 10,037,814, 2018 | 1 | 2018 |
High speed dynamic comparator MI El-Chammas US Patent 9,013,344, 2015 | 1 | 2015 |
Frontend Sampling Networks M El-Chammas High-Performance and High-Speed Pipelined ADCs, 57-90, 2023 | | 2023 |
Reference Generation M El-Chammas High-Performance and High-Speed Pipelined ADCs, 123-137, 2023 | | 2023 |
Overview of Pipelined ADCs M El-Chammas High-Performance and High-Speed Pipelined ADCs, 11-38, 2023 | | 2023 |
Correcting Pipelined ADC Errors M El-Chammas High-Performance and High-Speed Pipelined ADCs, 139-150, 2023 | | 2023 |
Pipelined ADC Topologies M El-Chammas High-Performance and High-Speed Pipelined ADCs, 39-55, 2023 | | 2023 |