| Delay locked loop H Lee US Patent 7,282,974, 2007 | 58 | 2007 |
| Semiconductor memory device for controlling output timing of data depending on frequency variation H Lee US Patent 7,027,336, 2006 | 58 | 2006 |
| Digital delay locked loop capable of correcting duty cycle and its method H Lee, JT Kwak US Patent 7,161,397, 2007 | 52 | 2007 |
| Delay locked loop with a function for implementing locking operation periodically during power down mode and locking operation method of the same HW Lee US Patent 7,388,415, 2008 | 44 | 2008 |
| A 3.57 Gb/s/pin low jitter all-digital DLL with dual DCC circuit for GDDR3 DRAM in 54-nm CMOS technology WJ Yun, HW Lee, D Shin, S Kim Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 19 (9 …, 2011 | 43 | 2011 |
| DLL circuit and method of controlling the same DS Shin, H Lee, WJ Yun US Patent 7,598,783, 2009 | 42* | 2009 |
| 17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces J Song, HW Lee, J Kim, S Hwang, C Kim Solid-State Circuits Conference-(ISSCC), 2015 IEEE International, 1-3, 2015 | 41* | 2015 |
| A 0.1-to-1.5 GHz 4.2 mW all-digital DLL with dual duty-cycle correction circuit and update gear circuit for DRAM in 66nm CMOS technology WJ Yun, HW Lee, D Shin, SD Kang, JY Yang, HO Lee, DU Lee, S Sim, ... Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical …, 2008 | 41 | 2008 |
| Delay locked loop apparatus WJ Yun, HW Lee US Patent 7,830,186, 2010 | 39 | 2010 |
| Register controlled delay locked loop and its control method JT Kwak, H Lee US Patent 7,088,159, 2006 | 39 | 2006 |
| A 1.0-ns/1.0-V delay-locked loop with racing mode and countered CAS latency controller for DRAM interfaces HW Lee, H Choi, BJ Shin, KH Kim, KW Kim, J Kim, KH Kim, JH Jung, ... Solid-State Circuits, IEEE Journal of 47 (6), 1436-1447, 2012 | 38 | 2012 |
| A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology HW Lee, KH Kim, YK Choi, JH Sohn, NK Park, KW Kim, C Kim, YJ Choi, ... Solid-State Circuits, IEEE Journal of 47 (1), 131-140, 2012 | 35 | 2012 |
| A 2.5 Gb/s/pin 256Mb GDDR3 SDRAM with series pipelined CAS latency control and dual-loop digital DLL DU Lee, HW Lee, KC Kwean, YK Choi, HU Moon, SW Kwack, SD Kang, ... 2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006 | 35 | 2006 |
| DLL circuit having duty cycle correction and method of controlling the same WJ Yun, HW Lee US Patent 7,821,310, 2010 | 33 | 2010 |
| Electronic system generating multi-phase clocks and training method thereof HW Lee US Patent App. 14/476,340, 2015 | 29* | 2015 |
| Duty cycle correcting circuit HW Lee, DS Shin, WJ YUN, HS Inc. US Patent 7,750,703, 2010 | 28* | 2010 |
| Delay locked loop and locking method thereof H Lee US Patent 6,943,602, 2005 | 27 | 2005 |
| Delay-locked loop apparatus and delay-locked method WJ Yun, HW Lee US Patent 7,560,963, 2009 | 23 | 2009 |
| Data output strobe signal generating circuit and semiconductor memory apparatus having the same WJ Yun, H Lee US Patent 7,633,324, 2009 | 20 | 2009 |
| High-Bandwidth Memory Interface C Kim, HW Lee, J Song Springer Science & Business Media, 2013 | 19 | 2013 |
Won-Joo (Ryan) YunCorporate VP, Samsung Electronics在 samsung.com 的电子邮件经过验证
