| Automated testing flow: The present and the future M Portolan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 24 | 2019 |
| A highly flexible hardened RTL processor core based on LEON2 M Portolan, R Leveugle IEEE Transactions on Nuclear Science 53 (4), 2069-2075, 2006 | 20 | 2006 |
| A novel test generation and application flow for functional access to IEEE 1687 instruments M Portolan 2016 21th IEEE European test symposium (ETS), 1-6, 2016 | 19 | 2016 |
| Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing TJ Chakraborty, CH Chiang, S Goyal, M Portolan, BG Van Treuren US Patent 7,962,885, 2011 | 19 | 2011 |
| Device and method for transmitting samples of a digital baseband signal M Portolan, L Roullet US Patent App. 14/412,503, 2015 | 18 | 2015 |
| Method and apparatus for position-based scheduling for JTAG systems M Portolan, B Van Treuren, S Goyal US Patent 8,775,884, 2014 | 18 | 2014 |
| Method and apparatus for virtual in-circuit emulation S Goyal, M Portolan, B Van Treuren US Patent 8,621,301, 2013 | 17 | 2013 |
| Method and apparatus for describing and testing a system-on-chip TJ Chakraborty, CH Chiang, S Goyal, M Portolan, BG Van Treuren US Patent 7,958,479, 2011 | 17 | 2011 |
| Method and apparatus for deferred scheduling for JTAG systems M Portolan, B Van Treuren, S Goyal US Patent 8,719,649, 2014 | 16 | 2014 |
| Method and apparatus for describing parallel access to a system-on-chip TJ Chakraborty, CH Chiang, S Goyal, M Portolan, BG Van Treuren US Patent 7,949,915, 2011 | 15 | 2011 |
| Method and apparatus for providing scan chain security S Goyal, M Portolan, B Van Treuren US Patent 8,495,758, 2013 | 14 | 2013 |
| Method and apparatus for system testing using multiple instruction types S Goyal, M Portolan, B Van Treuren US Patent 8,533,545, 2013 | 12 | 2013 |
| Method and apparatus for system testing using scan chain decomposition S Goyal, M Portolan, B Van Treuren US Patent App. 12/495,336, 2010 | 12 | 2010 |
| Apparatus and method for isolating portions of a scan path of a system-on-chip T Chakraborty, CH Chiang, S Goyal, M Portolan, BG Van Treuren US Patent 7,958,417, 2011 | 11 | 2011 |
| Apparatus and method for controlling dynamic modification of a scan path T Chakraborty, CH Chiang, S Goyal, M Portolan, BG Van Treuren US Patent 7,954,022, 2011 | 11 | 2011 |
| Dynamic authentication-based secure access to test infrastructure M Portolan, V Reynaud, P Maistri, R Leveugle 2020 IEEE European Test Symposium (ETS), 1-6, 2020 | 10 | 2020 |
| Executing IJTAG: are vectors enough? M Portolan, B Van Treuren, S Goyal IEEE Design & Test 30 (5), 15-25, 2013 | 10 | 2013 |
| Method and apparatus for system testing using multiple processors S Goyal, M Portolan, B Van Treuren US Patent 8,677,198, 2014 | 9 | 2014 |
| Modeling novel non-JTAG IEEE 1687-like architectures M Laisne, A Crouch, M Portolan, M Keim, HM von Staudt, M Abdalwahab, ... 2020 IEEE International Test Conference (ITC), 1-10, 2020 | 8 | 2020 |
| Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor K Chibani, M Ben-Jrad, M Portolan, R Leveugle 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC …, 2014 | 8 | 2014 |
