| Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates H Mertens, R Ritzenthaler, A Hikavyy, MS Kim, Z Tao, K Wostyn, SA Chew, ... 2016 IEEE symposium on VLSI technology, 1-2, 2016 | 206 | 2016 |
| Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates H Mertens, R Ritzenthaler, A Chasin, T Schram, E Kunnen, A Hikavyy, ... 2016 IEEE International Electron Devices Meeting (IEDM), 19.7. 1-19.7. 4, 2016 | 158 | 2016 |
| Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ... IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018 | 128 | 2018 |
| Vertically stacked gate-all-around Si nanowire transistors: Key process optimizations and ring oscillator demonstration H Mertens, R Ritzenthaler, V Pena, G Santoro, K Kenis, A Schulze, ... 2017 IEEE international electron devices meeting (IEDM), 37.4. 1-37.4. 4, 2017 | 124 | 2017 |
| Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack T Ernst, C Dupre, C Isheden, E Bernard, R Ritzenthaler, V Maffini-Alvaro, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 97 | 2006 |
| Self-heating on bulk FinFET from 14nm down to 7nm node D Jang, E Bury, R Ritzenthaler, MG Bardon, T Chiarella, K Miyaguchi, ... 2015 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2015 | 96 | 2015 |
| Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced vertical nanowires separation, new work function metal gate solutions, and DC/AC performance … R Ritzenthaler, H Mertens, V Pena, G Santoro, A Chasin, K Kenis, ... 2018 IEEE International Electron Devices Meeting (IEDM), 21.5. 1-21.5. 4, 2018 | 85 | 2018 |
| A model of fringing fields in short-channel planar and triple-gate SOI MOSFETs T Ernst, R Ritzenthaler, O Faynot, S Cristoloveanu IEEE transactions on electron devices 54 (6), 1366-1375, 2007 | 76 | 2007 |
| Forksheet FETs for advanced CMOS scaling: forksheet-nanosheet co-integration and dual work function metal gates at 17nm NP space H Mertens, R Ritzenthaler, Y Oniki, B Briggs, BT Chan, A Hikavyy, T Hopf, ... 2021 Symposium on VLSI Technology, 1-2, 2021 | 53 | 2021 |
| Experimental validation of self-heating simulations and projections for transistors in deeply scaled nodes E Bury, B Kaczer, P Roussel, R Ritzenthaler, K Raleva, D Vasileska, ... 2014 IEEE International Reliability Physics Symposium, XT. 8.1-XT. 8.6, 2014 | 53 | 2014 |
| Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high … H Mertens, R Ritzenthaler, H Arimura, J Franco, F Sebaai, A Hikavyy, ... 2015 Symposium on VLSI Technology (VLSI Technology), T142-T143, 2015 | 51 | 2015 |
| Lateral coupling and immunity to substrate effect in ΩFET devices R Ritzenthaler, S Cristoloveanu, O Faynot, C Jahan, A Kuriyama, ... Solid-state electronics 50 (4), 558-565, 2006 | 48 | 2006 |
| Performance Comparison of –Type Si Nanowires, Nanosheets, and FinFETs by MC Device Simulation FM Bufler, R Ritzenthaler, H Mertens, G Eneman, A Mocuta, N Horiguchi IEEE Electron Device Letters 39 (11), 1628-1631, 2018 | 47 | 2018 |
| New analysis method for time-dependent device-to-device variation accounting for within-device fluctuation M Duan, JF Zhang, Z Ji, WD Zhang, B Kaczer, T Schram, R Ritzenthaler, ... IEEE transactions on electron devices 60 (8), 2505-2511, 2013 | 40 | 2013 |
| Plasma doping and reduced crystalline damage for conformally doped fin field effect transistors J Woo Lee, Y Sasaki, M Ju Cho, M Togo, G Boccardi, R Ritzenthaler, ... Applied Physics Letters 102 (22), 2013 | 38 | 2013 |
| 3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors R Ritzenthaler, F Lime, O Faynot, S Cristoloveanu, B Iñiguez Solid-state electronics 65, 94-102, 2011 | 36 | 2011 |
| First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers A Vandooren, J Franco, Z Wu, B Parvais, W Li, L Witters, A Walke, L Peng, ... 2018 IEEE International Electron Devices Meeting (IEDM), 7.1. 1-7.1. 4, 2018 | 35 | 2018 |
| Buried power rail integration with FinFETs for ultimate CMOS scaling A Gupta, OV Pedreira, G Arutchelvan, H Zahedmanesh, K Devriendt, ... IEEE Transactions on Electron Devices 67 (12), 5349-5354, 2020 | 32 | 2020 |
| Analytical modeling of direct tunneling current through gate stacks for the determination of suitable high-k dielectrics for nanoscale double-gate MOSFETs G Darbandy, R Ritzenthaler, F Lime, I Garduno, M Estrada, A Cerdeira, ... Semiconductor science and technology 26 (4), 045002, 2011 | 31 | 2011 |
| Will strain be useful for 10nm quasi-ballistic FDSOI devices? An experimental study V Barral, T Poiroux, F Rochette, M Vinet, S Barraud, O Faynot, L Tosti, ... 2007 IEEE Symposium on VLSI Technology, 128-129, 2007 | 30 | 2007 |
