| The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 259 | 2020 |
| DRAMPower: Open-source DRAM power & energy estimation tool K Chandrasekar, C Weis, Y Li, B Akesson, N Wehn, K Goossens URL: http://www. drampower. info 22, 2012 | 200 | 2012 |
| Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ M Sadri, C Weis, N Wehn, L Benini Proceedings of the 10th FPGAworld Conference, 1-8, 2013 | 101 | 2013 |
| Exploiting expendable process-margins in DRAMs for run-time performance optimization K Chandrasekar, S Goossens, C Weis, M Koedam, B Akesson, N Wehn, ... 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 98 | 2014 |
| A 2.15 GBit/s turbo code decoder for LTE advanced base station applications T Ilnseher, F Kienle, C Weis, N Wehn 2012 7th International Symposium on Turbo Codes and Iterative Information …, 2012 | 79 | 2012 |
| DRAMSys: a flexible DRAM subsystem design space exploration framework M Jung, C Weis, N Wehn IPSJ Transactions on System and LSI Design Methodology 8, 63-74, 2015 | 74 | 2015 |
| Design space exploration for 3D-stacked DRAMs C Weis, N Wehn, L Igor, L Benini 2011 Design, Automation & Test in Europe, 1-6, 2011 | 65 | 2011 |
| Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted G Braun, E Plaettner, C Weis, A Jakobs US Patent 7,457,174, 2008 | 63 | 2008 |
| Approximate computing with partially unreliable dynamic random access memory-approximate DRAM M Jung, DM Mathew, C Weis, N Wehn Proceedings of the 53rd Annual Design Automation Conference, 1-4, 2016 | 56 | 2016 |
| Omitting refresh: A case study for commodity and wide i/o drams M Jung, É Zulian, DM Mathew, M Herrmann, C Brugger, C Weis, N Wehn Proceedings of the 2015 International Symposium on Memory Systems, 85-91, 2015 | 52 | 2015 |
| TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration M Jung, C Weis, N Wehn, K Chandrasekar Proceedings of the 2013 Workshop on Rapid Simulation and Performance …, 2013 | 52 | 2013 |
| Exploration and optimization of 3-D integrated DRAM subsystems C Weis, I Loi, L Benini, N Wehn IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 47 | 2013 |
| Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience A Herkersdorf, H Aliee, M Engel, M Glaß, C Gimmler-Dumont, J Henkel, ... Microelectronics Reliability 54 (6-7), 1066-1074, 2014 | 43 | 2014 |
| Reverse engineering of DRAMs: Row hammer with crosshair M Jung, CC Rheinländer, C Weis, N Wehn Proceedings of the Second International Symposium on Memory Systems, 471-476, 2016 | 42 | 2016 |
| Method and circuit arrangement for controlling write access to a semiconductor memory S Dietrich, T Hein, P Schroegmeier, C Weis US Patent 7,224,625, 2007 | 41 | 2007 |
| Energy optimization in 3D MPSoCs with wide-I/O DRAM using temperature variation aware bank-wise refresh M Sadri, M Jung, C Weis, N Wehn, L Benini 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014 | 38 | 2014 |
| Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs C Weis, M Jung, P Ehses, C Santos, P Vivet, S Goossens, M Koedam, ... 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 495-500, 2015 | 37 | 2015 |
| Towards variation-aware system-level power estimation of DRAMs: An empirical approach K Chandrasekar, C Weis, B Akesson, N Wehn, K Goossens Proceedings of the 50th Annual Design Automation Conference, 1-8, 2013 | 36 | 2013 |
| System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs K Chandrasekar, C Weis, B Akesson, N Wehn, K Goossens 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 236-241, 2013 | 35 | 2013 |
| A platform to analyze DDR3 DRAM’s power and retention time M Jung, DM Mathew, CC Rheinländer, C Weis, N Wehn IEEE Design & Test 34 (4), 52-59, 2017 | 33 | 2017 |
Norbert WehnUniversity of Kaiserslautern在 eit.uni-kl.de 的电子邮件经过验证
