| Introduction to high-level synthesis DD Gajski, L Ramachandran IEEE Design & Test of Computers 11 (4), 44-54, 1994 | 317 | 1994 |
| High-level transformations for minimizing syntactic variances V Chaiyakul, DD Gajski, L Ramachandran Proceedings of the 30th international Design Automation Conference, 413-418, 1993 | 127 | 1993 |
| An algorithm for array variable clustering L Ramachandran, DD Gajski, V Chaiyakul Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC, 262-266, 1994 | 109 | 1994 |
| An Algorithm for Component Selection in Performance Optimized Scheduling. L Ramachandran, D Gajski ICCAD, 92-95, 1991 | 77 | 1991 |
| System design methodologies: aiming at the 100 h design cycle DD Gajski, S Narayan, L Ramachandran, F Vahid, P Fung IEEE transactions on very large scale integration (VLSI) systems 4 (1), 70-82, 1996 | 52 | 1996 |
| 100-hour design cycle: A test case DD Gajski, L Ramachandran, P Fung, S Narayan, F Vahid Proc. Europ. Design Automation Conf. EURO-DAC, 1994 | 24 | 1994 |
| System and method for implementing the fast wavelet transform M Vafai, L Ramachandran, M Lempel US Patent 5,706,220, 1998 | 20 | 1998 |
| Minimizing syntactic variance with assignment decision diagrams V Chaiyakul, DD Gajski, L Ramachandran | 19 | 1992 |
| Method to derive edge extensions for wavelet transforms and inverse wavelet transforms M Lempel, M Vafai, L Ramachandran US Patent 5,828,849, 1998 | 18 | 1998 |
| Synthesis of functions and procedures in behavioral VHDL L Ramachandran, S Narayan, F Vahid, DD Gajski Proceedings of EURO-DAC 93 and EURO-VHDL 93-European Design Automation …, 1993 | 14 | 1993 |
| Semantics and synthesis of signals in behavioral VHDL L Ramachandran, F Vahid, S Narayan, DD Gajski | 12 | 1992 |
| System and method for implementation of inverse wavelet transforms L Ramachandran, M Lempel, M Vafai US Patent 6,182,102, 2001 | 9 | 2001 |
| Architectural tradeoffs in synthesis of pipelined controls L Ramachandran, DD Gajski Proceedings of EURO-DAC 93 and EURO-VHDL 93-European Design Automation …, 1993 | 8 | 1993 |
| Behavioral design assistant (BdA) user's manual: version 1.0 L Ramachandran, DD Gajski | 4 | 1994 |
| CHASSIS: a combined hardware selection and scheduling technique for performance driven synthesis L Ramachandran, DD Gajski | 4 | 1991 |
| The design process of behavioral synthesis from VHDL L Ramachandran, ND Holmes, DD Gajski | 2 | 1994 |
| Towards achieving an 100-hour Design Cycle: A test Case DD Gajski, L Ramachandran, P Fung, F Vahid, S Narayan | 2 | 1994 |
| VHDL synthesis system (VSS): user's manual, version 5.0 L Ramachandran, V Chaiyakul, DD Gajski | 2 | 1992 |
| CLSS-a workbench for control logic synthesis B Mitra, L Ramachandran, S Rajam, G Rajagopalan Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design, 219,220 …, 1991 | 1 | 1991 |
| Specification and design of multi-million gate SOCs R Chandra, PR Panda, J Henkel, S Parameswaran, L Ramachandran VLSI Design, International Conference on, 18-18, 2003 | | 2003 |
