| Inter-tier process-variation-aware monolithic 3-D NoC design space exploration S Musavvir, A Chatterjee, RG Kim, DH Kim, PP Pande IEEE Transactions on very large scale integration (VLSI) systems 28 (3), 686-699, 2019 | 16 | 2019 |
| Power management of monolithic 3D manycore chips with inter-tier process variations A Chatterjee, S Musavvir, RG Kim, JR Doppa, PP Pande ACM Journal on Emerging Technologies in Computing Systems (JETC) 17 (2), 1-19, 2021 | 5 | 2021 |
| Power, performance, and thermal trade-offs in M3D-enabled manycore chips S Musavvir, A Chatterjee, RG Kim, DH Kim, JR Doppa, PP Pande 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 5 | 2020 |
| Delay analysis of SWCNT bundle interconnect for different technology nodes S Musavvir, P Chowdhury, SM Mominuzzaman 2016 9th International Conference on Electrical and Computer Engineering …, 2016 | 1 | 2016 |
| Resource Management in Manycore Architecture: 3D NoC to Embedded Systems S Musavvir Washington State University, 2022 | | 2022 |
