| Trends of CPU, GPU and FPGA for high-performance computing M Vestias, H Neto 2014 24th International Conference on Field Programmable Logic and …, 2014 | 124 | 2014 |
| A survey of convolutional neural networks on edge with reconfigurable computing MP Véstias Algorithms 12 (8), 154, 2019 | 109 | 2019 |
| Moving deep learning to the edge MP Véstias, RP Duarte, JT de Sousa, HC Neto Algorithms 13 (5), 125, 2020 | 55 | 2020 |
| Decimal multiplier on FPGA using embedded binary multipliers HC Neto, MP Véstias 2008 International Conference on Field Programmable Logic and Applications …, 2008 | 43 | 2008 |
| Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers MP Véstias, HC Neto Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational …, 2010 | 42* | 2010 |
| Parallel decimal multipliers using binary multipliers MP Véstias, HC Neto 2010 VI Southern Programmable Logic Conference (SPL), 73-78, 2010 | 41 | 2010 |
| A full featured configurable accelerator for object detection with YOLO D Pestana, PR Miranda, JD Lopes, RP Duarte, MP Véstias, HC Neto, ... IEEE Access 9, 75864-75877, 2021 | 40 | 2021 |
| Predicting calcium in grape must and base wine by FT-NIR spectroscopy J Véstia, JM Barroso, H Ferreira, L Gaspar, AE Rato Food Chemistry 276, 71-76, 2019 | 36 | 2019 |
| Multi-core for K-means clustering on FPGA J Canilho, M Véstias, H Neto 2016 26th International Conference on Field Programmable Logic and …, 2016 | 33 | 2016 |
| Architectures and compilers to support reconfigurable computing JMP Cardoso, MP Vestístias XRDS: Crossroads, The ACM Magazine for Students 5 (3), 15-22, 1999 | 33 | 1999 |
| Parallel dot-products for deep learning on FPGA M Véstias, RP Duarte, JT de Sousa, H Neto 2017 27th International Conference on Field Programmable Logic and …, 2017 | 30 | 2017 |
| Double-precision gauss-jordan algorithm with partial pivoting on fpgas R Duarte, H Neto, M Véstias 2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009 | 28 | 2009 |
| Area and performance optimization of a generic network-on-chip architecture MP Véstias, HC Neto Proceedings of the 19th annual symposium on Integrated circuits and systems …, 2006 | 27 | 2006 |
| Co-synthesis of a configurable SoC platform based on a network on chip architecture MP Véstias, HC Neto Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 23 | 2006 |
| A fast and scalable architecture to run convolutional neural networks in low density FPGAs MP Véstias, RP Duarte, JT de Sousa, HC Neto Microprocessors and Microsystems 77, 103136, 2020 | 22 | 2020 |
| Lite-CNN: A high-performance architecture to execute CNNs in low density FPGAs M Véstias, RP Duarte, JT de Sousa, H Neto 2018 28th International Conference on Field Programmable Logic and …, 2018 | 22 | 2018 |
| Revisiting the Newton-Raphson iterative method for decimal division MP Vestias, HC Neto 2011 21st International Conference on Field Programmable Logic and …, 2011 | 20 | 2011 |
| Iterative decimal multiplication using binary arithmetic MP Véstias, HC Neto 2011 VII Southern Conference on Programmable Logic (SPL), 257-262, 2011 | 20 | 2011 |
| A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective H Cruz, M Véstias, J Monteiro, H Neto, RP Duarte Remote Sensing 14 (5), 1258, 2022 | 17 | 2022 |
| Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning MP Véstias, RP Duarte, JT de Sousa, HC Neto Electronics 8 (11), 1321, 2019 | 17 | 2019 |
Horacio NetoINESC-ID / IST, University of Lisbon在 inesc-id.pt 的电子邮件经过验证
