| Evolving priority rules for resource constrained project scheduling problem with genetic programming M Đumić, D Šišejković, R Čorić, D Jakobović Future Generation Computer Systems 86, 211-221, 2018 | 67 | 2018 |
| Challenging the security of logic locking schemes in the era of deep learning: A neuroevolutionary approach D Sisejkovic, F Merchant, LM Reimann, H Srivastava, A Hallawa, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 17 (3), 1-26, 2021 | 65 | 2021 |
| Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks D Sisejkovic, F Merchant, LM Reimann, R Leupers IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 42 | 2021 |
| Control-lock: Securing processor cores against software-controlled hardware trojans D Šišejković, F Merchant, R Leupers, G Ascheid, S Kegreiss Proceedings of the 2019 on Great Lakes Symposium on VLSI, 27-32, 2019 | 25 | 2019 |
| Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities D Sisejkovic, LM Reimann, E Moussavi, F Merchant, R Leupers IFIP/IEEE 29th International Conference on Very Large Scale Integration …, 2021 | 23 | 2021 |
| Immunological algorithms paradigm for construction of Boolean functions with good cryptographic properties S Picek, D Sisejkovic, D Jakobovic Engineering Applications of Artificial Intelligence 62, 320-330, 2017 | 22 | 2017 |
| Evolving cryptographic pseudorandom number generators S Picek, D Sisejkovic, V Rozic, B Yang, D Jakobovic, N Mentens International Conference on Parallel Problem Solving from Nature, 613-622, 2016 | 22 | 2016 |
| NeuroHammer: Inducing bit-flips in memristive crossbar memories F Staudigl, H Al Indari, D Schön, D Sisejkovic, F Merchant, JM Joseph, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022 | 20 | 2022 |
| Qflow: Quantitative information flow for security-aware hardware design in verilog LM Reimann, L Hanel, D Sisejkovic, F Merchant, R Leupers 2021 IEEE 39th International Conference on Computer Design (ICCD), 603-607, 2021 | 20 | 2021 |
| A Unifying Logic Encryption Security Metric D Šišejković, R Leupers, G Ascheid, S Metzner Proceedings of the 18th International Conference on Embedded Computer …, 2018 | 20 | 2018 |
| A secure hardware-software solution based on RISC-V, logic locking and microkernel D Šišejković, F Merchant, LM Reimann, R Leupers, M Giacometti, ... Proceedings of the 23th International Workshop on Software and Compilers for …, 2020 | 18 | 2020 |
| S-box pipelining using genetic algorithms for high-throughput AES implementations: How fast can we go? L Batina, D Jakobovic, N Mentens, S Picek, A De La Piedra, D Sisejkovic International Conference on Cryptology in India, 322-337, 2014 | 18 | 2014 |
| Inter-lock: Logic encryption for processor cores beyond module boundaries D Šišejković, F Merchant, R Leupers, G Ascheid, S Kegreiss 2019 IEEE European Test Symposium (ETS), 1-6, 2019 | 17 | 2019 |
| Scaling logic locking schemes to multi-module hardware designs D Šišejković, F Merchant, LM Reimann, R Leupers, S Kegreiß Architecture of Computing Systems–ARCS 2020: 33rd International Conference …, 2020 | 13 | 2020 |
| Vertical IP Protection of the Next-Generation Devices: Quo Vadis? S Rai, S Garg, C Pilato, V Herdt, E Moussavi, D Sisejkovic, R Karri, ... Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2021 | 9 | 2021 |
| Evolution of scheduling heuristics for the resource constrained scheduling problem D Šišejkovic University of Zagreb, Faculty Of Electrical Engineering and Computing, Zagreb, 2016 | 7 | 2016 |
| Andromeda: An fpga based risc-v mpsoc exploration framework F Merchant, D Sisejkovic, LM Reimann, K Yasotharan, T Grass, ... 2021 34th International Conference on VLSI Design and 2021 20th …, 2021 | 6 | 2021 |
| A critical evaluation of the paradigm shift in the design of logic encryption algorithms D Šišejković, F Merchant, R Leupers, G Ascheid, V Kiefer 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2019 | 6 | 2019 |
| Designing ML-resilient locking at register-transfer level D Sisejkovic, L Collini, B Tan, C Pilato, R Karri, R Leupers Proceedings of the 59th ACM/IEEE Design Automation Conference, 769-774, 2022 | 5 | 2022 |
| X-fault: Impact of faults on binary neural networks in memristor-crossbar arrays with logic-in-memory computation F Staudigl, KJX Sturm, M Bartel, T Fetz, D Sisejkovic, JM Joseph, ... 2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022 | 5 | 2022 |
Rainer LeupersRWTH Aachen在 ice.rwth-aachen.de 的电子邮件经过验证
