| Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET R Singh, K Aditya, SS Parihar, YS Chauhan, R Vega, TB Hook, A Dixit IEEE Electron Device Letters 39 (8), 1246-1249, 2018 | 57 | 2018 |
| BSIM compact model of quantum confinement in advanced nanosheet FETs A Dasgupta, SS Parihar, P Kushwaha, H Agarwal, MY Kao, S Salahuddin, ... IEEE Transactions on Electron Devices 67 (2), 730-737, 2020 | 49 | 2020 |
| Compact Model for Geometry Dependent Mobility in Nanosheet FETs A Dasgupta, SS Parihar, H Agarwal, P Kushwaha, YS Chauhan, C Hu IEEE Electron Device Letters 41 (3), 313-316, 2020 | 27 | 2020 |
| Compact modeling of negative-capacitance FDSOI FETs for circuit simulations CK Dabhi, SS Parihar, A Dasgupta, YS Chauhan IEEE Transactions on Electron Devices 67 (7), 2710-2716, 2020 | 21 | 2020 |
| Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K SS Parihar, VM van Santen, S Thomann, G Pahwa, YS Chauhan, ... IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | 11 | 2023 |
| Efficient Implementation of Max-Pooling Algorithm Exploiting History-Effect in Ferroelectric-FinFETs M Rafiq, SS Parihar, YS Chauhan, S Sahay IEEE Transactions on Electron Devices, 2022 | 8 | 2022 |
| BSIM4 4.8. 1 MOSFET model CK Dabhi, SS Parihar, H Agrawal, N Paydavosi, TH Morshed, DD Lu, ... Dept. Elect. Eng. Comput. Sci., Univ. California, Berkeley, CA, Tech. Rep …, 2017 | 8 | 2017 |
| Characterization and Global Parameter Extraction of bulk MOSFETs using BSIM-BULK Model SS Parihar, C Jha, R Singh, R Gurjar, A Dixit 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical …, 2018 | 5 | 2018 |
| A Comprehensive RF Characterization and Modeling Methodology for the 5nm Technology Node FinFETs SS Parihar, A Pampori, P Dwivedi, J Huang, W Wang, K Imura, C Hu, ... IEEE Journal of the Electron Devices Society, 2023 | 3 | 2023 |
| Analysis and Compact Modeling of Drain-Extended FinFET V Kumar, CK Dabhi, SS Parihar, YS Chauhan 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK …, 2019 | 3 | 2019 |
| Cryogenic Embedded System to Support Quantum Computing: From 5nm FinFET to Full Processor PR Genssler, F Klemme, SS Parihar, S Brandhofer, G Pahwa, I Polian, ... IEEE Transactions on Quantum Engineering, 2023 | 2 | 2023 |
| Design Automation for Cryogenic CMOS Circuits VM van Santen, M Walter, F Klemme, SS Parihar, G Pahwa, YS Chauhan, ... 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 2 | 2023 |
| Characterization and Modeling of 14-/16-nm FinFET-Based LDMOS A Kar, SS Parihar, JZ Huang, H Zhang, W Wang, K Imura, YS Chauhan IEEE Transactions on Electron Devices, 2023 | 2 | 2023 |
| Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs SS Parihar, G Pahwa, JZ Huang, W Wang, K Imura, C Hu, YS Chauhan 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2023 | 2 | 2023 |
| Self-Heating characterization and modeling of 5nm technology node FinFETs SS Parihar, JZ Huang, W Wang, K Imura, YS Chauhan 2022 Device Research Conference (DRC), 1-2, 2022 | 2 | 2022 |
| BSIM4 User Manual CK Dabhi, SS Parihar, H Agrawal, N Paydavosi, TH Morshed University of California, Berkeley, 2017 | 2 | 2017 |
| High-Frequency Characterization and Modeling of Low and High Voltage FinFETs for RF SoCs YS Chauhan, A Kar, SS Parihar, JZ Huang, H Zhang, W Wang, K Imura 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2023 | 1 | 2023 |
| Modeling and Benchmarking 5nm Ferroelectric FinFET from Room Temperature down to Cryogenic Temperatures S Singh Parihar, S Chatterjee, G Pahwa, Y Singh Chauhan, H Amrouch IEEE 23rd International Conference on Nanotechnology (NANO), 2023 | 1 | 2023 |
| Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction SS Parihar, G Pahwa, YS Chauhan, H Amrouch 2024 IEEE International Reliability Physics Symposium (IRPS), 1-7, 2024 | | 2024 |
| Small-Signal and Large-Signal RF Characterization and Modeling of Low and High Voltage FinFETs for 14/16 nm Technology Node SoCs A Kar, SS Parihar, JZ Huang, H Zhang, W Wang, K Imura, YS Chauhan IEEE Journal of the Electron Devices Society, 2024 | | 2024 |
Yogesh S. ChauhanFellow IEEE, FNAE, Professor-IIT Kanpur在 iitk.ac.in 的电子邮件经过验证
