| Using a reconfigurable L1 data cache for efficient version management in hardware transactional memory A Armejach, A Seyedi, R Titos-Gil, I Hur, OS Unsal, M Valero 2011 International Conference on Parallel Architectures and Compilation …, 2011 | 21 | 2011 |
| Double edge triggered feedback flip-flop in sub 100nm technology SH Rasouli, A Amirabadi, A Seyedi, A Afzali-Kusha Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 16 | 2006 |
| Circuit design of a dual-versioning L1 data cache for optimistic concurrency A Seyedi, A Armejach, A Cristal, OS Unsal, I Hur, M Valero Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011 | 14 | 2011 |
| Flexicache: Highly reliable and low power cache under supply voltage scaling G Yalcin, A Seyedi, OS Unsal, A Cristal High Performance Computing: First HPCLATAM-CLCAR Latin American Joint …, 2014 | 13 | 2014 |
| Double-edge triggered level converter flip-flop with feedback AS Seyedi, A Afzali-Kusha 2006 International Conference on Microelectronics, 44-47, 2006 | 13 | 2006 |
| NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs A Seyedi, V Karakostas, S Cosemans, A Cristal, M Nemirovsky, O Unsal Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale …, 2015 | 11 | 2015 |
| Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications with High Reliability Requirements A Seyedi, S Aunet, PG Kjeldsberg IEEE Access 10, 30624-30642, 2022 | 10 | 2022 |
| Circuit design of a novel adaptable and reliable L1 data cache A Seyedi, G Yalcin, OS Unsal, A Cristal Proceedings of the 23rd ACM international conference on Great lakes …, 2013 | 9 | 2013 |
| High Speed Low Gate Leakage Large Capacitive-Load Driver Circuits for Low-Voltage CMOS B Kheradmand-Boroujeni, A Seyyedi, A Afzali-Kusha International Conference on Microelectronics, 2005 | 9 | 2005 |
| Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications A Seyedi, S Aunet, PG Kjeldsberg 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and …, 2019 | 7 | 2019 |
| Low power and high performance clock delayed domino logic using saturated keeper A Amirabadi, A Chehelcheraghi, SH Rasouli, A Seyedi, A Afzai-Kusha 2006 IEEE International Symposium on Circuits and Systems, 4 pp.-3176, 2006 | 7 | 2006 |
| Clock gated static pulsed flip-flop (CGSPFF) in sub 100 nm technology AS Seyedi, SH Rasouli, A Amirabadi, A Afzali-Kusha IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and …, 2006 | 7 | 2006 |
| Novel SRAM bias control circuits for a low power L1 data cache A Seyedi, A Armejach, A Cristal, OS Unsal, M Valero NORCHIP 2012, 1-6, 2012 | 6 | 2012 |
| Low power low leakage clock gated static pulsed flip-flop AS Seyedi, SH Rasouli, A Amirabadi, A Afzali-Kusha 2006 IEEE International Symposium on Circuits and Systems, 4 pp.-3661, 2006 | 6 | 2006 |
| Circuit design of a dual-versioning L1 data cache A Seyedi, A Armejach, A Cristal, OS Unsal, I Hur, M Valero Integration 45 (3), 237-245, 2012 | 2 | 2012 |
| Comparing the Performance of a Low-Power High Speed Flip-Flop in Bulk and SOI Technologies B Forouzandeh, AS Seyedi Proceedings of the International Conference Mixed Design of Integrated …, 2006 | 2 | 2006 |
| Design of domino logic circuits by an optimization method AS Seyedi, SH Rasouli, A Amirabadi, A Afzali-Kusha, C Lucas, ... Proceedings of the International Conference Mixed Design of Integrated …, 2006 | 1 | 2006 |
| Computer Memory and Data Storage A Seyedi BoD–Books on Demand, 2024 | | 2024 |
| Introductory Chapter: Computer Memory and Data Storage A Seyedi Computer Memory and Data Storage, 2024 | | 2024 |
| System-Scenario Methodology to Design a Highly Reliable Radiation-Hardened Memory for Space Applications A Seyedi, PG Kjeldsberg, R Birkeland Computer Memory and Data Storage, 2023 | | 2023 |
