| RIJID: Random code injection to mask power analysis based side channel attacks JA Ambrose, RG Ragel, S Parameswaran Proceedings of the 44th annual Design Automation Conference, 489-492, 2007 | 83 | 2007 |
| MUTE-AES: A multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm JA Ambrose, S Parameswaran, A Ignjatovic 2008 IEEE/ACM International Conference on Computer-Aided Design, 678-684, 2008 | 61 | 2008 |
| Layer-based operations scheduling to optimise memory for CNN applications JA Ambrose, I Ahmed, Y Yachide, H Bokhari, J Peddersen, ... US Patent 10,740,674, 2020 | 56 | 2020 |
| Design and implementation of an operating system for composable processor sharing A Hansson, M Ekerhult, A Molnos, A Milutinovic, A Nelson, J Ambrose, ... Microprocessors and Microsystems 35 (2), 246-260, 2011 | 49 | 2011 |
| Advanced modes in AES: Are they safe from power analysis based side channel attacks? D Jayasinghe, R Ragel, JA Ambrose, A Ignjatovic, S Parameswaran 2014 IEEE 32nd International Conference on Computer Design (ICCD), 173-180, 2014 | 48 | 2014 |
| Processor design for soft errors: Challenges and state of the art T Li, JA Ambrose, R Ragel, S Parameswaran ACM Computing Surveys (CSUR) 49 (3), 1-44, 2016 | 35 | 2016 |
| A smart random code injection to mask power analysis based side channel attacks JA Ambrose, RG Ragel, S Parameswaran Proceedings of the 5th IEEE/ACM international conference on Hardware …, 2007 | 32 | 2007 |
| Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks JA Ambrose, RG Ragel, S Parameswaran, A Ignjatovic IET computers & digital techniques 5 (1), 1-15, 2011 | 30 | 2011 |
| RASTER: Runtime adaptive spatial/temporal error resiliency for embedded processors T Li, M Shafique, JA Ambrose, S Rehman, J Henkel, S Parameswaran Proceedings of the 50th Annual Design Automation Conference, 1-7, 2013 | 28 | 2013 |
| A composable, energy-managed, real-time MPSoC platform A Molnos, JA Ambrose, A Nelson, R Stefan, S Cotofana, K Goossens 2010 12th International Conference on Optimization of Electrical and …, 2010 | 28 | 2010 |
| Power analysis side channel attacks: The processor design-level context J Ambrose, A Ignjatovic, S Parameswaran (No Title), 2010 | 24 | 2010 |
| Side channel attacks in embedded systems: A tale of hostilities and deterrence JA Ambrose, RG Ragel, D Jayasinghe, T Li, S Parameswaran Sixteenth International Symposium on Quality Electronic Design, 452-459, 2015 | 21 | 2015 |
| DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems T Li, M Shafique, S Rehman, JA Ambrose, J Henkel, S Parameswaran 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 646-653, 2013 | 20 | 2013 |
| Overview and investigation of SEU detection and recovery approaches for FPGA-based heterogeneous systems E Cetin, O Diessel, T Li, JA Ambrose, T Fisk, S Parameswaran, ... FPGAs and Parallel Architectures for Aerospace Applications: Soft Errors and …, 2016 | 19 | 2016 |
| Quadseal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks D Jayasinghe, A Ignjatovic, JA Ambrose, R Ragel, S Parameswaran 2015 International Conference on Compilers, Architecture and Synthesis for …, 2015 | 19 | 2015 |
| Randomized instruction injection to counter power analysis attacks JA Ambrose, RG Ragel, S Parameswaran ACM Transactions on Embedded Computing Systems (TECS) 11 (3), 1-28, 2012 | 19 | 2012 |
| Improving ga-based noc mapping algorithms using a formal model VA Palaniveloo, JA Ambrose, A Sowmya 2014 IEEE Computer Society Annual Symposium on VLSI, 344-349, 2014 | 16 | 2014 |
| A double-width algorithmic balancing to prevent power analysis side channel attacks in aes A Arora, JA Ambrose, J Peddersen, S Parameswaran 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 76-83, 2013 | 16 | 2013 |
| Anatomy of differential power analysis for AES JA Ambrose, N Aldon, A Ignjatovic, S Parameswaran 2008 10th International Symposium on Symbolic and Numeric Algorithms for …, 2008 | 16 | 2008 |
| CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors T Li, M Shafique, S Rehman, S Radhakrishnan, R Ragel, JA Ambrose, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 707-712, 2013 | 13 | 2013 |
