| Double patterning layout decomposition for simultaneous conflict and stitch minimization K Yuan, JS Yang, D Pan Proceedings of the 2009 international symposium on Physical design, 107-114, 2009 | 156 | 2009 |
| TSV stress aware timing analysis with applications to 3D-IC layout optimization J Yang, K Athikulwongse, YJ Lee, SK Lim, DZ Pan Proceedings of the 47th Design Automation Conference, 803-806, 2010 | 146 | 2010 |
| Stress-driven 3D-IC placement with TSV keep-out zone and regularity study K Athikulwongse, A Chakraborty, JS Yang, DZ Pan, SK Lim 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 669-674, 2010 | 128 | 2010 |
| A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography JS Yang, K Lu, M Cho, K Yuan, DZ Pan 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 637-644, 2010 | 83 | 2010 |
| Overlay aware interconnect and timing variation modeling for double patterning technology JS Yang, DZ Pan 2008 IEEE/ACM International Conference on Computer-Aided Design, 488-493, 2008 | 50 | 2008 |
| Design for manufacturability and reliability for TSV-based 3D ICs DZ Pan, SK Lim, K Athikulwongse, M Jung, J Mitra, J Pak, M Pathak, ... 17th Asia and South Pacific Design Automation Conference, 750-755, 2012 | 40 | 2012 |
| Robust clock tree synthesis with timing yield optimization for 3D-ICs JS Yang, J Pak, X Zhao, SK Lim, DZ Pan 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 621-626, 2011 | 35 | 2011 |
| Dealing with IC manufacturability in extreme scaling B Yu, JR Gao, D Ding, Y Ban, J Yang, K Yuan, M Cho, DZ Pan Proceedings of the International Conference on Computer-Aided Design, 240-242, 2012 | 31 | 2012 |
| Integrated circuit devices and method of manufacturing the same S Rastogi, S Kuchanuri, R Azmat, P Park, CH Park, JS Yang, KY Chun US Patent 10,361,198, 2019 | 23 | 2019 |
| Impact of mechanical stress on the full chip timing for through-silicon-via-based 3-D ICs K Athikulwongse, JS Yang, DZ Pan, SK Lim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 23 | 2013 |
| Semiconductor devices and methods of manufacturing the same HJ Kim, CH Kim, JUN Hwi-Chan, CH Park, JS Yang, KY Chun US Patent 10,177,093, 2019 | 22 | 2019 |
| Layout method and semiconductor device IW OH, JS Yang, JH Lee, HJ Lee, SW Hwang US Patent App. 15/372,840, 2017 | 17 | 2017 |
| Layout optimizations for double patterning lithography DZ Pan, JS Yang, K Yuan, M Cho, Y Ban 2009 IEEE 8th International Conference on ASIC, 726-729, 2009 | 16 | 2009 |
| CAD for double patterning lithography DZ Pan, JS Yang, K Yuan, M Cho 2010 IEEE International Conference on Integrated Circuit Design and …, 2010 | 9 | 2010 |
| Semiconductor device and method of manufacturing the same Y Kim, JS Yang, HW Lee US Patent App. 16/270,214, 2020 | 8 | 2020 |
| Integrated circuit (IC) devices including cross gate contacts R Ranjan, D Sharma, S Kuchanuri, CH Park, JS Yang, KY Chun US Patent 10,546,855, 2020 | 8 | 2020 |
| Integrated circuit including standard cell and method of fabricating the integrated circuit R Azmat, S Rastogi, CH Park, JS Yang, KY Chun US Patent 11,461,521, 2022 | 7 | 2022 |
| Semiconductor device, method of designing a layout of a semiconductor device, and method of manufacturing a semiconductor device S Rastogi, S Kuchanuri, CH Park, JS Yang US Patent 10,474,783, 2019 | 7 | 2019 |
| Methods of fabricating a semiconductor device I Oh, H Lee, J Yang US Patent 9,871,122, 2018 | 7 | 2018 |
| Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis JS Yang, JY Kim, JH Choi, MH Yoo, JT Kong Fourth International Symposium on Quality Electronic Design, 2003 …, 2003 | 7 | 2003 |
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at Austin在 ece.utexas.edu 的电子邮件经过验证
