| A Highly Reliable and Energy-Efficient Triple-Node-Upset-Tolerant Latch Design CI Kumar, B Anand IEEE Transactions on Nuclear Science 66 (10), 2196-2206, 2019 | 55 | 2019 |
| A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design CI Kumar, B Anand IEEE Transactions on Device and Materials Reliability 20 (1), 58-66, 2019 | 27 | 2019 |
| Design of highly reliable energy-efficient SEU tolerant 10T SRAM cell CI Kumar, B Anand Electronics Letters 54 (25), 1423-1424, 2018 | 15 | 2018 |
| High performance energy efficient radiation hardened latch for low voltage applications CI Kumar, A Bulusu Integration 66, 119-127, 2019 | 11 | 2019 |
| An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN D Kushwaha, A Joshi, CI Kumar, N Gupta, S Miryala, RV Joshi, ... IEEE Transactions on Circuits and Systems II: Express Briefs 69 (4), 2311-2315, 2022 | 9 | 2022 |
| Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications R Shekhar, CI Kumar Integration 87, 176-181, 2022 | 7 | 2022 |
| Time-Borrowing Flip-Flop Architecture for Multi-Stage Timing Error Resilience in DVFS Processors A Ghosh, MS Naseem, CI Kumar 2021 International Conference on Intelligent Technologies (CONIT), 1-7, 2021 | 4 | 2021 |
| A novel energy-efficient self-correcting methodology employing INWE CI Kumar, A Sharma, S Miryala, A Bulusu 2016 13th International Conference on Synthesis, Modeling, Analysis and …, 2016 | 4 | 2016 |
| A novel low power noise tolerant high performance dynamic feed through logic design technique M Pattanaik, S Parashar, CI Kumar, A Chouhan, V Mahor 2011 International Symposium on Electronic System Design, 118-123, 2011 | 4 | 2011 |
| High Performance CMOS Voltage Level Shifters Design for Low Voltage Applications A Kapoor, CS Jha, A Thapar, CI Kumar 2023 International Conference for Advancement in Technology (ICONAT), 1-6, 2023 | 2 | 2023 |
| Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications CI Kumar, A Chaudhary, S Upadhyaya Integration 95, 102133, 2024 | 1 | 2024 |
| A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches CI Kumar, I Bhatia, AK Sharma, D Sehgal, HS Jatana, A Bulusu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (9 …, 2019 | 1 | 2019 |
| An energy-efficient variation aware self-correcting latch CI Kumar, AK Sharma, R Partap, A Bulusu Microelectronics Journal 84, 67-78, 2019 | 1 | 2019 |
| An efficient design technique for high performance dynamic feedthrough logic with enhanced noise tolerance S Parashar, CI Kumar, M Pattanaik 2011 IEEE Computer Society Annual Symposium on VLSI, 49-53, 2011 | 1 | 2011 |
| Highly Robust High Speed Low Power Single Node Upset Hardened Latch P Mandal, P Kumar, SV Singh, CI Kumar 2024 IEEE Third International Conference on Power Electronics, Intelligent …, 2024 | | 2024 |
| A High Performance and Low Power Subthreshold Voltage Level Shifter Design A Kapoor, A Thapar, CS Jha, CI Kumar 2024 37th International Conference on VLSI Design and 2024 23rd …, 2024 | | 2024 |
| An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design CI Kumar Journal of Circuits, Systems and Computers 31 (07), 2250125, 2022 | | 2022 |
| A Single Node Upset Hardened Latch Design in NTV Regime CI Kumar 2021 IEEE 4th International Conference on Computing, Power and Communication …, 2021 | | 2021 |
| Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability CI Kumar, A Bulusu 2018 14th Conference on Ph. D. Research in Microelectronics and Electronics …, 2018 | | 2018 |
Bulusu AnandIndian Institute of Technology Roorkee在 ece.iitr.ac.in 的电子邮件经过验证
