| Matrix Code Based Multiple Error Correction Technique for N-bit Memory Data MS Sunita, VSK Bhaaskaran International Journal of VLSI Design & Communication Systems 4 (1), 29, 2013 | 9 | 2013 |
| Encoder and Adaptive Decoder for a (15, 6, 2) DEC-TED BCH Code P Rao, P Babshet, RA Babu, MS Sunita 2020 IEEE 17th India Council International Conference (INDICON), 1-6, 2020 | 4 | 2020 |
| Study of Different Adders Using Full Swing Gate Diffusion Input D Sahoo, A Deshpande, MS Sunitha 2020 5th IEEE International Conference on Recent Advances and Innovations in …, 2020 | 4 | 2020 |
| Comparative analysis of FinFET and planar MOSFET SRAMs K Pradeep, B Mohith, KP Manjunath, MS Sunita 2020 International SoC Design Conference (ISOCC), 11-12, 2020 | 4 | 2020 |
| Pipeline Architecture for fast decoding of BCH Codes for NOR Flash Memory KBVS Sunita M. S, Chiranth V, Akash H. C ARPN Journal of Engineering and Applied Sciences 10 (8), 3397-3304, 2015 | 4 | 2015 |
| Error Detection and Correction in Embedded Memories Using Cyclic Code SM Sunita, VSK Bhaaskaran, D Hegde, P Dhareshwar Proceedings of International Conference on VLSI, Communication, Advanced …, 2013 | 4 | 2013 |
| Multiple Bit Error Correction Codes for Memories in Satellites BN Tejas, KS Kumar, SM Sunita 2022 IEEE 7th International conference for Convergence in Technology (I2CT), 1-6, 2022 | 2 | 2022 |
| A high efficiency, fast response buck converter for low voltage applications MS Sunita, BS Rakshitha, K Sankirthana, S Tantry 2019 IEEE Asia Pacific Conference on Postgraduate Research in …, 2019 | 2 | 2019 |
| DESIGN AND COMPARISON OF RISC PROCESSORS USING DIFFERENT ALU ARCHITECTURES MS Sunitha, BG Hegde, DN Hegde | 2 | 2013 |
| A Novel Voltage Based In-Memory Computing Architecture using STT-MRAM SS KV, S Gowda, MS Sunita 2023 IEEE 8th International Conference for Convergence in Technology (I2CT), 1-7, 2023 | 1 | 2023 |
| Low Power and High-performance Ternary Content Addressable Memory using Carbon Nanotube FET P Kumar, KAK Jain, AR PS, MS Sunita 2023 IEEE 8th International Conference for Convergence in Technology (I2CT), 1-6, 2023 | 1 | 2023 |
| Analysis of Switched Capacitor Buck Converter using Sampling Frequency Control Method MS Sunita, DA RB, LK Shetty, S Tantry 2021 IEEE 8th Uttar Pradesh Section International Conference on Electrical …, 2021 | 1 | 2021 |
| Adaptive ON-Time Boost Converter in 45nm for Solar Cell Applications MS Sunita, T Somashekhar, S Tantry 2021 18th International SoC Design Conference (ISOCC), 135-136, 2021 | 1 | 2021 |
| A low noise low power Operational Transconducatance Amplifier for biomedical applications SV Manturshettar, MS Sunita 2019 IEEE 16th India Council International Conference (INDICON), 1-4, 2019 | 1 | 2019 |
| Single-Ended Sub-threshold 9T SRAM Cell With Ground Cut-Off S Adarsh, M Tanmay, MS Sunita 2019 China Semiconductor Technology International Conference (CSTIC), 1-4, 2019 | 1 | 2019 |
| Magnetic ram based filter design for low power signal processing in IoT applications S Rao, KS Shashikanth, R Srinivas, MS Sunita 2017 14th IEEE India Council international conference (INDICON), 1-6, 2017 | 1 | 2017 |
| Modelling and Analysis of Adaptive ON-Time Controlled Boost Converter Using Verilog-A S MS, P Gowda, S Lakshman, T Moolchandani, S Tantry Australian Journal of Electrical and Electronics Engineering, 1-13, 2024 | | 2024 |
| Pulsed Latch Based Pipelined LFSR for Cybersecurity Applications S Patil, BV Vaishnavi, S Gangadhara, S Naik, MS Sunita 2024 IEEE 4th International Conference on VLSI Systems, Architecture …, 2024 | | 2024 |
| Optimization of Analog Circuit Placement: A Graph Neural Network Approach Y HK, S K, S Biyani, S MS Proceedings of the 2024 10th International Conference on Computing and …, 2024 | | 2024 |
| A Novel Error Correction Code with Reduced Memory Utilization and Increased Accuracy P Vasudev, SS Murthy, MS Sunita 2021 IEEE International Conference on Electronics, Computing and …, 2021 | | 2021 |
