Design of Efficient Full Adder for Low Power Applications PYA Khan, S Rambabu International Journal and Magazine of Engineering, Technology, Management …, 2017 | 3 | 2017 |
Implementation of DDR SDRAM Memory Controller for embedded SOC B Naresh, S Rambabu, GL Narayana International Journal of Advanced Trends in Computer Science and Engineering …, 2016 | 2 | 2016 |
High Performance and Low Noise BCD Adder Circuit Design Using Rate Sensing Keeper S Rambabu, B Sruthi, K Sreelakshmi, V Ramyakrishna, S Althaf, ... International Journal of Advanced Research in Electrical, Electronics and …, 2015 | 2 | 2015 |
Performance Analysis of Nano Transistor Based Binary and Ternary Logic Gates C Venkataiah, S Rambabu International Journal of Integrated Engineering 16 (2), 66-75, 2024 | 1 | 2024 |
Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits C Venkataiah, M Jayamma, S Rambabu, LM MK, LH Alzubaidi, S Mishra E3S Web of Conferences 391, 01221, 2023 | 1 | 2023 |
ARM controller and EEG based drowsiness tracking and controlling during driving B Naresh, S Rambabu, DK Basha International Journal of Reconfigurable and Embedded Systems (IJRES) 6, 127-32, 2018 | 1 | 2018 |
Effective Ternary Full Adder Cells for Nanoelectronics Using CNTFET Technology G Mahendra, BA Himabindu, S Rambabu, AM Vardhan, GC Priya 2024 IEEE North Karnataka Subsection Flagship International Conference …, 2024 | | 2024 |
Design of an Efficient Full Adder for Low Power Applications S Rambabu, PYA Khan | | |
An Efficient Low Power Ripple Carry Adder for Ultra Applications MR Babu, D Mahendra, S Rambabu | | |
Implementation of an Efficient Ripple Carry Adder by Low Power Techniques for Ultra Applications S Sindhuri, R Sravani, S Rambabu | | |