REACT: Read/write error rate aware coding technique for emerging STT-MRAM caches E Aliagha, AMH Monazzah, H Farbeh IEEE Transactions on Magnetics 55 (5), 1-8, 2019 | 23 | 2019 |
A-CACHE: Alternating cache allocation to conduct higher endurance in NVM-based caches H Farbeh, AMH Monazzah, E Aliagha, E Cheshmikhani IEEE Transactions on Circuits and Systems II: Express Briefs 66 (7), 1237-1241, 2018 | 21 | 2018 |
Energy efficient design of coarse-grained reconfigurable architectures: Insights, trends and challenges E Aliagha, D Göhringer 2022 International Conference on Field-Programmable Technology (ICFPT), 1-11, 2022 | 8 | 2022 |
Hardware/software co-design of 2d THz SAR imaging for FPGA-based systems-on-chip A Kamaleldin, E Aliagha, A Batra, M Wiemeler, T Kaiser, D Göhringer 2022 Fifth International Workshop on Mobile Terahertz Systems (IWMTS), 1-5, 2022 | 3 | 2022 |
Acceleration of 2D SAR Imaging on FPGA by Reducing off-chip Memory Accesses E Aliagha, A Kamaleldin, A Batra, T Nalapat, M Wiemeler, T Kaiser, ... 2023 Sixth International Workshop on Mobile Terahertz Systems (IWMTS), 1-5, 2023 | 2 | 2023 |
Investigating the Impact of Non-Volatile Memories on Energy-Efficiency of Coarse-Grained Reconfigurable Architectures E Aliagha, V Iskandar, S Enseleit, D Göhringer 2023 26th Euromicro Conference on Digital System Design (DSD), 748-755, 2023 | | 2023 |