关注
Chi-Lun Lo
Chi-Lun Lo
未知所在单位机构
在 ee.ntu.edu.tw 的电子邮件经过验证
标题
引用次数
引用次数
年份
A 4.5 mW CT Self-CoupledModulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation
CY Ho, C Liu, CL Lo, HC Tsai, TC Wang, YH Lin
IEEE Journal of Solid-State Circuits 50 (12), 2870-2879, 2015
862015
A 23 mW, 73 dB dynamic range, 80 MHz BW continuous-time delta-sigma modulator in 20 nm CMOS
S Ho, CL Lo, J Ru, J Zhao
IEEE Journal of Solid-State Circuits 50 (4), 908-919, 2015
862015
A 64-fJ/Conv.-Step Continuous-Time Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital Truncator
HC Tsai, CL Lo, CY Ho, YH Lin
IEEE journal of solid-state circuits 48 (11), 2637-2648, 2013
572013
NB-IoT and GNSS all-in-one system-on-chip integrating RF transceiver, 23-dBm CMOS power amplifier, power management unit, and clock management system for low cost solution
J Lee, J Han, CL Lo, J Lee, W Kim, S Kim, B Kang, J Han, S Jung, ...
IEEE Journal of Solid-State Circuits 55 (12), 3400-3413, 2020
442020
A 75.1 dB SNDR 840MS/s CT ΔΣ modulator with 30MHz bandwidth and 46.4 fJ/conv FOM in 55nm CMOS
CL Lo, CY Ho, HC Tsai, YH Lin
2013 Symposium on VLSI Circuits, C60-C61, 2013
242013
A GPS/Galileo SoC with adaptive in-band blocker cancellation in 65nm CMOS
CH Wu, WC Tsai, CG Tan, CN Chen, KI Li, JL Hsu, CL Lo, HH Chen, ...
2011 IEEE International Solid-State Circuits Conference, 462-464, 2011
232011
10.1 A 116μ W 104.4 dB-DR 100.6 dB-SNDR CT Δ∑ audio ADC using tri-level current-steering DAC with gate-leakage compensated off-transistor-based bias noise filter
C Lo, J Lee, Y Lim, Y Yoon, H Hwang, J Lee, MY Choi, M Lee, S Oh, J Lee
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 164-166, 2021
202021
System and method for measuring the DC-transfer characteristic of an analog-to-digital converter
FOT Eynde, N Egan, K Muhammad, TY Lo, CL Lo, MA Ashburn
US Patent 9,584,146, 2017
152017
A 1.2 V 64fJ/conversion-step continuous-time ΣΔ modulator using asynchronous SAR quantizer and digital ΣΔ truncator
HC Tsai, CL Lo, CY Ho, YH Lin
2012 IEEE Asian Solid State Circuits Conference (A-SSCC), 241-244, 2012
132012
Digitally-corrected analog-to-digital converters
K Muhammad, CL Lo, FOT Eynde, MA Ashburn Jr, TY Lo
US Patent 9,461,660, 2016
112016
Low-noise DC offset calibration circuit and related receiver stage
CL Lo, YH Lin
US Patent 7,956,680, 2011
102011
Method and apparatus for excess loop delay compensation in delta-sigma modulator
CL Lo, S Ho
US Patent App. 15/112,691, 2017
92017
Sigma-delta modulators with excess loop delay compensation
CY Ho, CL Lo, HC Tsai, YH Lin
US Patent 8,791,848, 2014
92014
30.2 NB-IoT and GNSS all-in-one system-on-chip integrating RF transceiver, 23dBm CMOS power amplifier, power management unit and clock management system for low-cost solution
J Lee, J Han, C Lo, J Lee, W Kim, S Kim, B Kang, J Han, S Jung, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 462-464, 2020
62020
A 1.04-4V, digital-intensive dual-mode BLE 5.0/IEEE 802.15. 4 transceiver SoC with extended range in 28nm CMOS
NS Kim, MG Kim, A Verma, G Seol, S Kim, S Lee, C Lo, J Han, I Jo, C Kim, ...
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 271-274, 2019
52019
Operational amplifier circuits
HC Tsai, CL Lo, CY Ho, YH Lin
US Patent 8,890,611, 2014
52014
A blocker-tolerant direct sampling receiver for wireless multi-channel communication in 14nm FinFET CMOS
B Sung, C Lo, J Lee, S Jung, S Kim, J Jung, S Bae, Y Cho, Y Lim, D Choi, ...
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 165-168, 2019
32019
A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOS
J Lee, J Lee, C Lo, J Lee, IY Lee, B Han, S Oh, T Cho
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 5-8, 2017
32017
AMPLIFIER, FULLY-DIFFERENTIAL AMPLIFIER AND DELTA-SIGMA MODULATOR
CY Ho, CL Lo, HC Tsai, YH Lin
US Patent 20,130,154,863, 2013
32013
Sigma-delta ADC with dither
FOT Eynde, CL Lo, MA Ashburn
US Patent 9,385,745, 2016
22016
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