| A secure camouflaged threshold voltage defined logic family B Erbagci, C Erbagci, NEC Akkaya, K Mai 2016 IEEE International Symposium on Hardware Oriented Security and Trust …, 2016 | 81 | 2016 |
| A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD NEC Akkaya, B Erbagci, K Mai 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 128-130, 2018 | 27 | 2018 |
| A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm B Erbagci, NEC Akkaya, C Teegarden, K Mai 2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015 | 16 | 2015 |
| Secure chip odometers using intentional controlled aging NEC Akkaya, B Erbagci, K Mai 2018 IEEE International Symposium on Hardware Oriented Security and Trust …, 2018 | 13 | 2018 |
| A DPA-resistant self-timed three-phase dual-rail pre-charge logic family NEC Akkaya, B Erbagci, R Carley, K Mai 2015 IEEE International Symposium on Hardware Oriented Security and Trust …, 2015 | 11 | 2015 |
| Combatting IC counterfeiting using secure chip odometers NEC Akkaya, B Erbagci, K Mai 2017 IEEE International Electron Devices Meeting (IEDM), 39.5. 1-39.5. 4, 2017 | 7 | 2017 |
| A secure camouflaged logic family using post-manufacturing programming with a 3.6 GHz adder prototype in 65nm CMOS at 1V nominal VDD. IEEE International Solid-State Circuits … NE Akkaya, B Erbagci, K Mai DOI 10, 128-130, 2018 | 5 | 2018 |
| An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS B Erbagci, NEC Akkaya, C Erbagci, K Mai ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC), 65-68, 2019 | 4 | 2019 |
| A 135.6 Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology NEC Akkaya, G Chan, HJ Liao, Y Wang, J Chang 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 3 | 2022 |
| Secure hardware-entangled field programmable gate arrays B Erbagci, NEC Akkaya, M Bhargava, R Dondero, K Mai Journal of Parallel and Distributed Computing 131, 81-96, 2019 | 3 | 2019 |
| A compact energy-efficient pseudo-static camouflaged logic family P Mohan, NEC Akkaya, B Erbagci, K Mai 2018 IEEE International Symposium on Hardware Oriented Security and Trust …, 2018 | 3 | 2018 |
| A 32kb secure cache memory with dynamic replacement mapping in 65nm bulk CMOS B Erbagci, F Liu, C Cakir, NEC Akkaya, R Lee, K Mai 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2015 | 3 | 2015 |
| MEMORY DEVICES WITH BACKSIDE BOOST CAPACITOR AND METHODS FOR FORMING THE SAME NEC Akkaya, M Sinangil, Y Wang, JT Chang US Patent App. 17/835,652, 2023 | 1 | 2023 |
| COMPUTE-IN-MEMORY CELL H Fujiwara, H Mori, W Zhao, C Lee, NEC Akkaya, M Sinangil US Patent App. 17/855,089, 2023 | | 2023 |
| BACK SIDE POWER SUPPLY INTERCONNECT ROUTING NEC Akkaya, M Sinangil, Y Wang, JT Chang US Patent App. 17/661,386, 2023 | | 2023 |
| Compute-In-Memory-Based Floating-Point Processor R Naous, K Akarvardar, M Sinangil, YD Chih, S Adham, NEC Akkaya, ... US Patent App. 17/825,036, 2023 | | 2023 |
| 18-743 Project: Low Power & Energy AES Implementations NEC Akkaya, R Carley | | |
| 18-743 Project: Low Power AES Implementations NEC Akkaya, R Carley | | |
