关注
Dr. M. Sultan M. Siddiqui
Dr. M. Sultan M. Siddiqui
R&D Manager II, SYNOPSYS
在 synopsys.com 的电子邮件经过验证
标题
引用次数
引用次数
年份
SRAM radiation hardening through self-refresh operation and error correction
MSM Siddiqui, S Ruchi, L Van Le, T Yoo, IJ Chang, TTH Kim
IEEE Transactions on Device and Materials Reliability 20 (2), 468-474, 2020
192020
A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI
MSM Siddiqui, ZC Lee, TTH Kim
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (10 …, 2021
102021
Integrated Circuit for Storing Data
SM Siddiqui, S Sharad, H Vats, A Khanuja
US Patent App. 14/828,364, 2016
102016
A 10T SRAM Cell with Enhanced Read Sensing Margin and Weak NMOS Keeper for Large Signal Sensing to Improve VDDMIN
M Sultan M Siddiqui, SK Sharma, S Porwal, KB Pannalal, S Kumar
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019
92019
A low-power ternary content addressable memory (TCAM) with segmented and non-segmented matchlines
M. Sultan M. Siddiqui, Sonika, GS Visweswaran
TENCON 2008-2008 IEEE Region 10 Conference, 1-5, 2008
72008
A reaction-diffusion model to capture disparity selectivity in primary visual cortex
MSM Siddiqui, B Bhaumik
PloS one 6 (10), e24997, 2011
62011
Mitigating write disturbance in dual port 8T SRAM
MSM Siddiqui, S Srivastav, DR Wanjul, M Suthar, S Kumar
US Patent 10,510,402, 2019
52019
An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI
ZC Lee, MSM Siddiqui, ZH Kong, TTH Kim
European Solid-State Circuits Conference, ESSCIRC Conference 2016: 42nd, 437-440, 2016
52016
Two phase write scheme to improve low voltage write ability in dedicated read and write port SRAM memories
M. Sultan M. Siddiqui, Shailendra Sharad, Hemant Vats, Amit Khanuja
US Patent 9,842,642, 2017
32017
A Study on Surface Slant Encoding in V1
MSM Siddiqui, B Bhaumik
Frontiers in System Neuroscience, 7:87. doi: 10.3389/fnsys., 2013
32013
Reaction-diffusion based model to develop binocular simple cells in visual cortex along with cortical maps
MSM Siddiqui, B Bhaumik
The 2010 International Joint Conference on Neural Networks (IJCNN), 1-8, 2010
32010
An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI
ZC Lee, MSM Siddiqui, ZH Kong, TTH Kim
IEEE Journal of Solid-State Circuits 54 (7), 2091-2101, 2019
22019
A 7-Nm dual port 8T SRAM with duplicated inter-port write data to mitigate write disturbance
MSM Siddiqui, S Srivastav, DR Wanjul, M Suthar, S Kumar
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
22018
A Radiation Hardened SRAM with Self-refresh and Compact Error Correction
M. Sultan M. Siddiqui, R. Sharma, V. L. Le, T. Yoo, I.-J. Chang, T. Kim
15th International SoC Design Conference (ISOCC), 2018
22018
Enhanced read sensing margin for SRAM cell arrays
MSM Siddiqui, SK Sharma, S Kumar, RK Shrivastava
US Patent 11,532,352, 2022
12022
Enhanced read sensing margin and minimized VDD for SRAM cell arrays
MSM Siddiqui, SK Sharma, S Porwal, KB Pannalal, S Kumar
US Patent 11,062,766, 2021
12021
A 16kb Column-based Split Cell-VSS, Data-Aware Write-Assisted 9T Ultra-Low Voltage SRAM with Enhanced Read Sensing Margin in 28nm FDSOI
MSM Siddiqui, ZC Lee, TTH Kim
IEEE Asian Solid State Circuit Conference, ASSCC Conference 2017, 2017
12017
Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs
M Sultan, M Siddiqui, S Sharad, Y Sharma, A Khanuja
2015 28th International Conference on VLSI Design, 176-180, 2015
12015
MODELING DISPARITY AND SURFACE SLANT SELECTIVITY IN PRIMARY VISUAL CORTEX
MSM SIDDIQUI
Indian Institute of Technology Delhi, 2012
2012
Interrelation between binocular disparity and other feature maps of V1 using Kohonen’s SOFM algorithm
MSM Siddiqui, MK Garg, B Bhaumik
BMC Neuroscience 11 (Suppl 1), P81, 2010
2010
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