| 14.5 A 1.22 ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S TH Tsai, MS Yuan, CH Chang, CC Liao, CC Li, RB Staszewski 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 49 | 2015 |
| Masking circuit and time-to-digital converter comprising the same TH Tsai US Patent 9,270,290, 2016 | 21 | 2016 |
| Phase-locked loop start up circuit CH Chen, MH Chou, TH Tsai US Patent 9,112,507, 2015 | 21 | 2015 |
| System and method for RC calibration using phase and frequency FW Kuo, TH Tsai, JL Chen US Patent 8,314,652, 2012 | 17 | 2012 |
| A 0.2 GHz to 4GHz Hybrid PLL (ADPLL/charge-pump-PLL) in 7nm FinFET CMOS featuring 0.619 PS integrated jitter and 0.6 US settling time at 2.3 mW TH Tsai, RB Sheen, CH Chang, RB Staszewski 2018 IEEE Symposium on VLSI Circuits, 183-184, 2018 | 14 | 2018 |
| Digitally controlled oscillator TH Tsai US Patent 9,496,882, 2016 | 14 | 2016 |
| A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8–19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS CC Li, TH Tsai, MS Yuan, CC Liao, CH Chang, TC Huang, HY Liao, ... 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 14 | 2016 |
| Phase lock loop (PLL) with gain control TH Tsai, TY Hung, CH Chen, MS Yuan US Patent 7,786,771, 2010 | 14 | 2010 |
| A hybrid-PLL (ADPLL/charge-pump PLL) using phase realignment with 0.6-us settling, 0.619-ps integrated jitter, and− 240.5-dB FoM in 7-nm FinFET TH Tsai, RB Sheen, CH Chang, KCH Hsieh, RB Staszewski IEEE Solid-State Circuits Letters 3, 174-177, 2020 | 12 | 2020 |
| Automatic detection of change in PLL locking trend TH Tsai, CH Chang US Patent 9,853,807, 2017 | 12 | 2017 |
| A Cascaded PLL (LC-PLL+ RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and-72dB Reference Spur TH Tsai, RB Sheen, SY Hsu, YT Chang, CH Chang, RB Staszewski 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 9 | 2022 |
| Hybrid phase lock loop TH Tsai, RB Sheen, CH Chang, CH Hsieh US Patent 10,164,649, 2018 | 9 | 2018 |
| Fractional realignment techniques for PLLs TH Tsai, RB Sheen, CH Chang, CH Hsieh US Patent 10,784,872, 2020 | 8 | 2020 |
| Real time automatic and background calibration at embedded duty cycle correlation M Li, TH Tsai, MH Chou, MS Yuan, CH Chang US Patent 9,148,135, 2015 | 8 | 2015 |
| A compact transformer-based fractional-N ADPLL in 10-nm FinFET CMOS CC Li, MS Yuan, CC Liao, CH Chang, YT Lin, TH Tsai, TC Huang, ... IEEE Transactions on Circuits and Systems I: Regular Papers 68 (5), 1881-1891, 2021 | 7 | 2021 |
| Embedded PLL phase noise measurement based on a PFD/CP MASH 1-1-1 ΔΣ time-to-digital converter in 7nm CMOS MH Chou, YT Chang, TH Tsai, TC Lu, CC Liao, HY Kuo, RB Sheen, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 6 | 2020 |
| Phase locked loop TH Tsai US Patent 9,257,998, 2016 | 5 | 2016 |
| Optimization methodology and apparatus for wide-swing current mirror with wide current range TH Tsai US Patent 8,847,572, 2014 | 5 | 2014 |
| Skew sensitive calculation for misalignment from multi patterning CH Chang, MS Yuan, TH Tsai US Patent 8,589,831, 2013 | 5 | 2013 |
| A 0.1–3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector YC Liu, WZ Chen, MH Chou, TH Tsai, YW Lee, MS Yuan Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013 | 5 | 2013 |
Robert Bogdan StaszewskiUniversity College Dublin (UCD)在 ucd.ie 的电子邮件经过验证
Robert Bogdan StaszewskiUniversity College Dublin (UCD)在 ucd.ie 的电子邮件经过验证
Alvin LokeIntel Corporation (San Diego)在 alumni.stanford.edu 的电子邮件经过验证