High resolution FPGA DPWM based on variable clock phase shifting A de Castro, E Todorovich IEEE Transactions on Power Electronics 25 (5), 1115-1119, 2009 | 63 | 2009 |
Low-power FSMs in FPGA: Encoding alternatives G Sutter, E Todorovich, S López-Buedo, E Boemo Integrated Circuit Design. Power and Timing Modeling, Optimization and …, 2002 | 61 | 2002 |
FPGA implementations of BCD multipliers G Sutter, E Todorovich, G Bioul, M Vazquez, JP Deschamps 2009 International Conference on Reconfigurable Computing and FPGAs, 36-41, 2009 | 42 | 2009 |
Genetic algorithms and fuzzy control: a practical synergism for industrial applications G Acosta, E Todorovich Computers in Industry 52 (2), 183-195, 2003 | 42 | 2003 |
Resolution analysis of switching converter models for hardware-in-the-loop O Goni, A Sanchez, E Todorovich, A de Castro IEEE Transactions on Industrial Informatics 10 (2), 1162-1170, 2013 | 33 | 2013 |
Accelerating embedded image processing for real time: a case study S Pedre, T Krajník, E Todorovich, P Borensztejn Journal of Real-Time Image Processing 11 (2), 349-374, 2016 | 32 | 2016 |
DPWM based on FPGA clock phase shifting with time resolution under 100 ps A De Castro, E Todorovich 2008 IEEE Power Electronics Specialists Conference, 3054-3059, 2008 | 30 | 2008 |
FSM decomposition for low power in FPGA G Sutter, E Todorovich, S Lopez-Buedo, E Boemo Field-Programmable Logic and Applications: Reconfigurable Computing Is Going …, 2002 | 26 | 2002 |
Introducing programmable logic to undergraduate engineering students in a digital electronics course E Todorovich, JA Marone, M Vázquez IEEE Transactions on Education 55 (2), 255-262, 2011 | 23 | 2011 |
Statistical power estimation for FPGAs E Todorovich, E Boemo, F Angarita, J Vails International Conference on Field Programmable Logic and Applications, 2005 …, 2005 | 21 | 2005 |
A tool for activity estimation in FPGAs E Todorovich, M Gilabert, G Sutter, S López-Buedo, E Boemo Field-Programmable Logic and Applications: Reconfigurable Computing Is Going …, 2002 | 21 | 2002 |
Exploring the limits of floating-point resolution for hardware-in-the-loop implemented with fpgas A Sanchez, E Todorovich, A De Castro Electronics 7 (10), 219, 2018 | 18 | 2018 |
A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA S Pedre, T Krajník, E Todorovich, P Borensztejn 2012 VIII Southern Conference on Programmable Logic, 1-8, 2012 | 15 | 2012 |
End-user low-power alternatives at topological and physical levels. Some examples on FPGAs E Todorovich, G Sutter, N Acosta, E Boemo, S López-Buedo Proc. DCIS'2000, 18-23, 2000 | 15 | 2000 |
Real-time speckle image processing E Todorovich, AL Dai Pra, LI Passoni, M Vázquez, E Cozzolino, F Ferrara, ... Journal of Real-Time Image Processing 11, 535-545, 2016 | 14 | 2016 |
Improvements for the applicability of power-watermarking to embedded IP cores protection: E-coreIPP L Parrilla, E Castillo, E Todorovich, A García, DP Morales, G Botella Digital Signal Processing 44, 110-122, 2015 | 12 | 2015 |
La pandemia de las redes sociales E Todorovich RADI, Empresas y Servicios de Ingeniería 9 (17), 2021 | 10 | 2021 |
Impact of the hardened floating-point cores on HIL technology A Sanchez, E Todorovich, A De Castro Electric Power Systems Research 165, 53-59, 2018 | 10 | 2018 |
Experiences applying OVM 2.0 to an 8B/10B RTL design O Cadenas, E Todorovich 2009 5th Southern Conference on Programmable Logic (SPL), 1-8, 2009 | 9 | 2009 |
Hardware/software co-design for real time embedded image processing: A case study S Pedre, T Krajník, E Todorovich, P Borensztejn Progress in Pattern Recognition, Image Analysis, Computer Vision, and …, 2012 | 7 | 2012 |