| 16.2 A 76fsrms Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced … J Kim, H Yoon, Y Lim, Y Lee, Y Cho, T Seong, J Choi 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 258-260, 2019 | 68 | 2019 |
| A low-jitter and fractional-resolution injection-locked clock multiplier using a DLL-based real-time PVT calibrator with replica-delay cells M Kim, S Choi, T Seong, J Choi IEEE Journal of Solid-State Circuits 51 (2), 401-411, 2015 | 50 | 2015 |
| A low-jitter and low-reference-spur ring-VCO-based switched-loop filter PLL using a fast phase-error correction technique Y Lee, T Seong, S Yoo, J Choi IEEE Journal of Solid-State Circuits 53 (4), 1192-1202, 2017 | 44 | 2017 |
| A 320-fs RMS Jitter and–75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC T Seong, Y Lee, S Yoo, J Choi IEEE Journal of Solid-State Circuits 54 (9), 2501-2512, 2019 | 39 | 2019 |
| An ultra-low-jitter, mmW-band frequency synthesizer based on digital subsampling PLL using optimally spaced voltage comparators J Kim, Y Lim, H Yoon, Y Lee, H Park, Y Cho, T Seong, J Choi IEEE Journal of Solid-State Circuits 54 (12), 3466-3477, 2019 | 37 | 2019 |
| 17.3 A −58dBc-Worst-Fractional-Spur and −234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator … T Seong, Y Lee, C Hwang, J Lee, H Park, KJ Lee, J Choi 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 270-272, 2020 | 34 | 2020 |
| A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for PLLs Y Lee, M Kim, T Seong, J Choi IEEE Transactions on Circuits and Systems I: Regular Papers 62 (3), 635-644, 2014 | 27 | 2014 |
| 32.1 A 365fsrms-Jitter and-63dBc-Fractional Spur 5.3 GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third-Order Nonlinearity Cancelation and a Probability-Density … H Park, C Hwang, T Seong, Y Lee, J Choi 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 442-444, 2021 | 26 | 2021 |
| A− 242dB FOM and− 75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC T Seong, Y Lee, S Yoo, J Choi 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 396-398, 2018 | 22 | 2018 |
| 30.9 A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope … S Yoo, S Choi, Y Lee, T Seong, Y Lim, J Choi 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 490-492, 2019 | 20 | 2019 |
| A− 242-dB FOM and− 71-dBc reference spur ring-VCO-based ultra-low-jitter switched-loop-filter PLL using a fast phase-error correction technique T Seong, Y Lee, S Yoo, J Choi 2017 Symposium on VLSI Circuits, C186-C187, 2017 | 20 | 2017 |
| A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability … C Hwang, H Park, Y Lee, T Seong, J Choi IEEE Journal of Solid-State Circuits 57 (9), 2841-2855, 2022 | 19 | 2022 |
| A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator S Yoo, S Choi, Y Lee, T Seong, Y Lim, J Choi IEEE Journal of Solid-State Circuits 56 (1), 298-309, 2020 | 19 | 2020 |
| 17.1 A −240dB-FoMjitter and −115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged … Y Lee, T Seong, J Lee, C Hwang, H Park, J Choi 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 266-268, 2020 | 18 | 2020 |
| A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Using a Single-VCO-Based Edge-Racing Time Quantizer J Lee, J Bang, Y Lim, S Yoo, Y Lee, T Seong, J Choi IEEE Solid-State Circuits Letters 2 (12), 305-308, 2019 | 13 | 2019 |
| Self-sustaining water-motion sensor platform for continuous monitoring of frequency and amplitude dynamics D Shin, T Seong, J Choi, W Choi Nano Energy 35, 179-188, 2017 | 12 | 2017 |
| A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector H Park, C Hwang, T Seong, J Choi IEEE Journal of Solid-State Circuits 57 (12), 3527-3537, 2022 | 11 | 2022 |
| Analysis and Design of a Core-Size-Scalable Low Phase Noise -VCO for Multi-Standard Cellular Transceivers T Seong, JJ Kim, J Choi IEEE Transactions on Circuits and Systems I: Regular Papers 62 (3), 781-790, 2015 | 11 | 2015 |
| A 188fsrms-Jitter and −243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing … C Hwang, H Park, T Seong, J Choi 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 378-380, 2022 | 10 | 2022 |
| 32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique J Kim, Y Jo, Y Lim, T Seong, H Park, S Yoo, Y Lee, S Choi, J Choi 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 448-450, 2021 | 9 | 2021 |
Jaehyouk ChoiAssociate Professor of Seoul National University在 snu.ac.kr 的电子邮件经过验证
