| Machine learning based framework to predict performance evaluation of on-chip networks A Kumar, B Talawar 2018 Eleventh International Conference on Contemporary Computing (IC3), 1-6, 2018 | 24 | 2018 |
| Traffic engineered NoC for streaming applications B Talwar, B Amrutur Microprocessors and Microsystems 37 (3), 333-344, 2013 | 12 | 2013 |
| Power and performance analysis of 3D network-on-chip architectures B Halavar, B Talawar Computers & Electrical Engineering 83, 106592, 2020 | 11 | 2020 |
| YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAs P Prasad, K Parane, B Talawar 2018 31st International Conference on VLSI Design and 2018 17th …, 2018 | 11 | 2018 |
| GPU implementation of non-local maximum likelihood estimation method for denoising magnetic resonance images AHK Upadhya, B Talawar, J Rajan Journal of Real-Time Image Processing, 1-12, 2016 | 11 | 2016 |
| Latency, power and performance trade-offs in network-on-chips by link microarchitecture exploration B Talwar, S Kulkarni, B Amrutur 2009 22nd International Conference on VLSI Design, 163-168, 2009 | 10 | 2009 |
| Parallel iterative hill climbing algorithm to solve TSP on GPU P Yelmewad, B Talawar Concurrency and Computation: Practice and Experience 31 (7), e4974, 2019 | 9 | 2019 |
| FPGA based NoC simulation acceleration framework supporting adaptive routing K Parane, P Prabhu, B Talawar 2018 IEEE International Conference on Electronics, Computing and …, 2018 | 9 | 2018 |
| On the cache behavior of splash-2 benchmarks on arm and alpha processors in gem5 full system simulator B Vikas, B Talawar 2014 3rd International Conference on Eco-friendly Computing and …, 2014 | 9 | 2014 |
| LBNoC: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA K Parane, B Talawar ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (1 …, 2020 | 8 | 2020 |
| Design of an adaptive and reliable network on chip router architecture using FPGA K Parane, BMP Prasad, B Talawar 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2019 | 8 | 2019 |
| A System-C based microarchitectural exploration framework for latency, power and performance trade-offs of on-chip Interconnection Networks B Talwar, B Amrutur Network on Chip Architectures, 30, 2008 | 8 | 2008 |
| A method for resource and service discovery in MANETs B Talwar, P Venkataram, LM Patnaik Wireless Personal Communications 41, 301-323, 2007 | 8 | 2007 |
| Extending BookSim2. 0 and HotSpot6. 0 for power, performance and thermal evaluation of 3D NoC architectures B Halavar, U Pasupulety, B Talawar Simulation Modelling Practice and Theory 96, 101929, 2019 | 7 | 2019 |
| Parallel version of local search heuristic algorithm to solve capacitated vehicle routing problem P Yelmewad, B Talawar Cluster Computing 24, 3671-3692, 2021 | 6 | 2021 |
| FPGA friendly NoC simulation acceleration framework employing the hard blocks BMP Prasad, K Parane, B Talawar Computing, 1-23, 2021 | 6 | 2021 |
| An efficient FPGA-based network-on-chip simulation framework utilizing the hard blocks BM Prabhu Prasad, K Parane, B Talawar Circuits, Systems, and Signal Processing 39 (10), 5247-5271, 2020 | 6 | 2020 |
| High-performance NoCs employing the DSP48E1 blocks of the Xilinx FPGAs P Prasad, K Parane, B Talawar 20th international symposium on quality electronic design (ISQED), 163-169, 2019 | 6 | 2019 |
| Trace-driven simulation and design space exploration of network-on-chip topologies on FPGA GS Sangeetha, V Radhakrishnan, P Prasad, K Parane, B Talawar 2018 8th International Symposium on Embedded Computing and System Design …, 2018 | 6 | 2018 |
| Accurate performance analysis of 3d mesh network on chip architectures B Halavar, B Talawar 2018 IEEE International Conference on Electronics, Computing and …, 2018 | 6 | 2018 |
Prabhu Prasad B MAssistant Professor, IIIT Dharwad在 iiitdwd.ac.in 的电子邮件经过验证
