| Cache side-channel attacks and time-predictability in high-performance critical real-time systems D Trilla, C Hernandez, J Abella, FJ Cazorla Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 50 | 2018 |
| Selene: Self-monitored dependable platform for high-performance safety-critical systems C Hernandez, J Flieh, R Paredes, CA Lefebvre, I Allende, J Abella, ... 2020 23rd euromicro conference on digital system design (DSD), 370-377, 2020 | 28 | 2020 |
| De-RISC: the first RISC-V space-grade platform for safety-critical systems NJ Wessman, F Malatesta, J Andersson, P Gomez, M Masmano, ... 2021 IEEE space computing conference (SCC), 17-26, 2021 | 27 | 2021 |
| SafeSU: an extended statistics unit for multicore timing interference G Cabo, F Bas, R Lorenzo, D Trilla, S Alcaide, M Moretó, C Hernández, ... 2021 IEEE European Test Symposium (ETS), 1-4, 2021 | 19 | 2021 |
| SafeDE: a flexible diversity enforcement hardware module for light-lockstepping F Bas, S Alcaide, R Lorenzo, G Cabo, G Gil, O Sala, F Mazzocchetti, ... 2021 IEEE 27th International Symposium on On-Line Testing and Robust System …, 2021 | 16 | 2021 |
| De-RISC–Dependable real-time infrastructure for safety-critical computer systems F Gómez, M Masmano, V Nicolau, J Andersson, J Le Rhun, D Trilla, ... Ada user journal 41 (2), 107-112, 2020 | 11 | 2020 |
| SafeTI: a hardware traffic injector for mpsoc functional and timing validation O Sala, S Alcaide, G Cabo, F Bas, R Lorenzo, P Benedicte, D Trilla, G Gil, ... 2021 IEEE 27th international symposium on on-line testing and robust system …, 2021 | 9 | 2021 |
| Resilient random modulo cache memories for probabilistically-analyzable real-time systems D Trilla, C Hernandez, J Abella, FJ Cazorla 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System …, 2016 | 9 | 2016 |
| Novia: A framework for discovering non-conventional inline accelerators D Trilla, JD Wellman, A Buyuktosunoglu, P Bose MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 8 | 2021 |
| Worst-case energy consumption: A new challenge for battery-powered critical devices D Trilla, C Hernandez, J Abella, FJ Cazorla IEEE Transactions on Sustainable Computing 6 (3), 522-530, 2019 | 6 | 2019 |
| Improving early design stage timing modeling in multicore based real-time systems D Trilla, J Jalle, M Fernandez, J Abella, FJ Cazorla 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS …, 2016 | 6 | 2016 |
| Multi-vehicle map fusion using GNU radio EA Sisbot, A Vega, A Paidimarri, JD Wellman, A Buyuktosunoglu, P Bose, ... Proceedings of the GNU Radio Conference 4 (1), 2019 | 5 | 2019 |
| Aging assessment and design enhancement of randomized cache memories D Trilla, C Hernandez, J Abella, FJ Cazorla IEEE Transactions on Device and Materials Reliability 17 (1), 32-41, 2017 | 5 | 2017 |
| Modeling the impact of process variations in worst-case energy consumption estimation D Trilla, C Hernandez, J Abella, FJ Cazorla 2019 22nd Euromicro Conference on Digital System Design (DSD), 601-605, 2019 | 2 | 2019 |
| Randomization for safer, more reliable and secure, high-performance automotive processors D Trilla, FJ Cazorla, C Hernandez, J Abella IEEE Design & Test 36 (6), 39-47, 2019 | 2 | 2019 |
| An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior D Trilla, C Hernandez, J Abella, FJ Cazorla 2019 22nd Euromicro Conference on Digital System Design (DSD), 538-545, 2019 | 1 | 2019 |
| Enterprise-Class Cache Compression Design A Buyuktosunoglu, D Trilla, B Abali, D Berger, C Walters, JS Lee 2024 IEEE International Symposium on High-Performance Computer Architecture …, 2024 | | 2024 |
| A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management, and Flexible NoC-Based Data Orchestration MC Dos Santos, T Jia, J Zuckerman, M Cochet, D Giri, E Loscalzo, ... IEEE International Solid-State Circuits Conference, 2024 | | 2024 |
| Non-functional considerations of time-randomized processor architectures D Trilla Rodríguez Universitat Politècnica de Catalunya, 2020 | | 2020 |
| Modelling bus contention during system early design stages D Trilla, C Hernandez, J Abella, FJ Cazorla 2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES …, 2017 | | 2017 |
Jaume AbellaBarcelona Supercomputing Center (BSC)在 bsc.es 的电子邮件经过验证
