| A study on the use of performance counters to estimate power in microprocessors R Rodrigues, A Annamalai, I Koren, S Kundu IEEE Transactions on Circuits and Systems II: Express Briefs 60 (12), 882-886, 2013 | 95 | 2013 |
| Performance per watt benefits of dynamic core morphing in asymmetric multicores R Rodrigues, A Annamalai, I Koren, S Kundu, O Khan 2011 International conference on parallel architectures and compilation …, 2011 | 56 | 2011 |
| An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs A Annamalai, R Rodrigues, I Koren, S Kundu Proceedings of the 22nd international conference on Parallel architectures …, 2013 | 52 | 2013 |
| Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing R Rodrigues, A Annamalai, I Koren, S Kundu ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (1 …, 2013 | 25 | 2013 |
| Scalable thread scheduling in asymmetric multicores for power efficiency R Rodrigues, A Annamalai, I Koren, S Kundu 2012 IEEE 24th international symposium on computer architecture and high …, 2012 | 24 | 2012 |
| Dynamic thread scheduling in asymmetric multicores to maximize performance-per-watt A Annamalai, R Rodrigues, I Koren, S Kundu 2012 IEEE 26th International Parallel and Distributed Processing Symposium …, 2012 | 22 | 2012 |
| Reducing energy per instruction via dynamic resource allocation and voltage and frequency adaptation in asymmetric multicores A Annamalai, R Rodrigues, I Koren, S Kundu 2014 IEEE Computer Society Annual Symposium on VLSI, 436-441, 2014 | 11 | 2014 |
| A study on polymorphing superscalar processor dynamically to improve power efficiency S Srinivasan, R Rodrigues, A Annamalai, I Koren, S Kundu 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 46-51, 2013 | 7 | 2013 |
| A system-level solution for managing spatial temperature gradients in thinned 3D ICs A Annamalai, R Kumar, A Vijayakumar, S Kundu International Symposium on Quality Electronic Design (ISQED), 88-95, 2013 | 5 | 2013 |
| A low-power instruction replay mechanism for design of resilient microprocessors R Rodrigues, A Annamalai, S Kundu ACM Transactions on Embedded Computing Systems (TECS) 13 (4), 1-23, 2014 | 3 | 2014 |
| On dynamic polymorphing of a superscalar core for improving energy efficiency S Srinivasan, R Rodrigues, A Annamalai, I Koren, S Kundu 2013 IEEE 31st International Conference on Computer Design (ICCD), 495-498, 2013 | 1 | 2013 |
| A dynamic reconfiguration framework to maximize performance/power in asymmetric multicore processors A Annamalai | 1 | 2013 |
| Using loop exit prediction to accelerate or suppress loop mode of a processor A Annamalai, M Evers, A Thyagarajan, A Jarvis US Patent 11,256,505, 2022 | | 2022 |
| Branch target buffer with early return prediction A Thyagarajan, M Evers, A Annamalai US Patent 11,055,098, 2021 | | 2021 |
| Using loop exit prediction to accelerate or suppress loop mode of a processor A Annamalai, M Evers, A Thyagarajan, A Jarvis US Patent 10,915,322, 2021 | | 2021 |
| Low latency synchronization for operation cache and instruction cache fetching and decoding instructions M Evers, DB Tavare, AT Venkatachar, A Annamalai, DA Priore, ... US Patent 10,896,044, 2021 | | 2021 |
Sandip KunduUniversity of Massachusetts在 ecs.umass.edu 的电子邮件经过验证
