Efficient parallelization of 5G-PUSCH on a scalable RISC-V many-core processor M Bertuletti, Y Zhang, A Vanelli-Coralli, L Benini 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 7 | 2023 |
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit … G Paulin, P Scheffler, T Benz, M Cavalcante, T Fischer, M Eggimann, ... 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2024 | 3 | 2024 |
Soft tiles: Capturing physical implementation flexibility for tightly-coupled parallel processing clusters G Paulin, M Cavalcante, P Scheffler, L Bertaccini, Y Zhang, F Gürkaynak, ... 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 44-49, 2022 | 3 | 2022 |
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster M Bertuletti, S Riedel, Y Zhang, A Vanelli-Coralli, L Benini International Conference on Embedded Computer Systems, 241-254, 2023 | 1 | 2023 |
Algorithm and Hardware Implementation for Generation of Low Power SIC Test Sequences B Cao, D Wen, Z Li, Y Zhang 2015 Fifth International Conference on Instrumentation and Measurement …, 2015 | 1 | 2015 |
TeraPool-SDR: An 1.89 TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios Y Zhang, M Bertuletti, S Riedel, M Cavalcante, A Vanelli-Coralli, L Benini GLSVLSI '24: Proceedings of the Great Lakes Symposium on VLSI 2024, 86–91, 2024 | | 2024 |
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication M Perotti, Y Zhang, M Cavalcante, E Mustafa, L Benini 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2024 | | 2024 |