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Yichao Zhang
Yichao Zhang
Ph.D Student, ETH Zurich
在 iis.ee.ethz.ch 的电子邮件经过验证 - 首页
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Efficient parallelization of 5G-PUSCH on a scalable RISC-V many-core processor
M Bertuletti, Y Zhang, A Vanelli-Coralli, L Benini
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023
72023
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit …
G Paulin, P Scheffler, T Benz, M Cavalcante, T Fischer, M Eggimann, ...
2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2024
32024
Soft tiles: Capturing physical implementation flexibility for tightly-coupled parallel processing clusters
G Paulin, M Cavalcante, P Scheffler, L Bertaccini, Y Zhang, F Gürkaynak, ...
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 44-49, 2022
32022
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster
M Bertuletti, S Riedel, Y Zhang, A Vanelli-Coralli, L Benini
International Conference on Embedded Computer Systems, 241-254, 2023
12023
Algorithm and Hardware Implementation for Generation of Low Power SIC Test Sequences
B Cao, D Wen, Z Li, Y Zhang
2015 Fifth International Conference on Instrumentation and Measurement …, 2015
12015
TeraPool-SDR: An 1.89 TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios
Y Zhang, M Bertuletti, S Riedel, M Cavalcante, A Vanelli-Coralli, L Benini
GLSVLSI '24: Proceedings of the Great Lakes Symposium on VLSI 2024, 86–91, 2024
2024
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication
M Perotti, Y Zhang, M Cavalcante, E Mustafa, L Benini
2024 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2024
2024
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