| Hybrid memory cube new DRAM architecture increases density and performance J Jeddeloh, B Keeth 2012 symposium on VLSI technology (VLSIT), 87-88, 2012 | 559 | 2012 |
| Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and … B Keeth US Patent 6,029,250, 2000 | 458 | 2000 |
| Method and apparatus for memory array compressed data testing B Keeth, TA Manning, CG Martin, KM Pierce, WE Fister, KJ Ryan, TR Lee, ... US Patent 5,935,263, 1999 | 448 | 1999 |
| DRAM sense amplifier for low voltages L Forbes, B Keeth US Patent 6,741,104, 2004 | 403 | 2004 |
| Memory system having synchronous-link DRAM (SLDRAM) devices and controller DB Gustavson, DV James, HA Wiggers, PB Gillingham, CM O'connell, ... US Patent 6,442,644, 2002 | 394 | 2002 |
| Clock vernier adjustment B Keeth US Patent 6,016,282, 2000 | 343 | 2000 |
| Signal delivery in stacked device B Keeth, M Hiatt, TR Lee, M Tuttle, R Advani, JF Schreck US Patent 8,106,520, 2012 | 293 | 2012 |
| DRAM circuit design: fundamental and high-speed topics B Keeth, RJ Baker, B Johnson, F Lin John Wiley & Sons, 2007 | 260 | 2007 |
| Synchronous clock generator including a compound delay-locked loop RM Harrison, B Keeth US Patent 6,011,732, 2000 | 248 | 2000 |
| Digitline architecture for dynamic memory B Keeth US Patent 6,661,041, 2003 | 207 | 2003 |
| Adjustable output driver circuit having parallel pull-up and pull-down elements B Keeth US Patent 5,838,177, 1998 | 195 | 1998 |
| High speed IC package configuration DJ Corisis, B Keeth US Patent 6,103,547, 2000 | 191 | 2000 |
| Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same B Keeth US Patent 6,430,696, 2002 | 185 | 2002 |
| Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device B Johnson, B Keeth, TA Manning US Patent 6,697,926, 2004 | 183 | 2004 |
| Low skew differential receiver with disable feature B Keeth, RJ Baker US Patent 6,256,234, 2001 | 181 | 2001 |
| Optical interconnect in high-speed memory systems RJ Baker, B Keeth US Patent 7,941,056, 2011 | 167 | 2011 |
| Adjustable output driver circuit B Keeth US Patent 5,949,254, 1999 | 164 | 1999 |
| Calibration technique for memory devices B Johnson, B Keeth US Patent 6,434,081, 2002 | 162 | 2002 |
| Method and apparatus for adjusting the timing of signals over fine and coarse ranges B Keeth, TA Manning US Patent 6,101,197, 2000 | 158 | 2000 |
| Multi-bank memory input/output line selection B Keeth, TA Manning US Patent 5,870,347, 1999 | 156 | 1999 |
