| A highly resilient routing algorithm for fault-tolerant NoCs D Fick, A DeOrio, G Chen, V Bertacco, D Sylvester, D Blaauw 2009 Design, Automation & Test in Europe Conference & Exhibition, 21-26, 2009 | 328 | 2009 |
| Vicis: A reliable network for unreliable silicon D Fick, A DeOrio, J Hu, V Bertacco, D Blaauw, D Sylvester Proceedings of the 46th Annual Design Automation Conference, 812-817, 2009 | 246 | 2009 |
| Event-driven gate-level simulation with GP-GPUs D Chatterjee, A DeOrio, V Bertacco Proceedings of the 46th Annual Design Automation Conference, 557-562, 2009 | 138 | 2009 |
| A reliable routing architecture and algorithm for NoCs A DeOrio, D Fick, V Bertacco, D Sylvester, D Blaauw, J Hu, G Chen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 134 | 2012 |
| Ariadne: Agnostic reconfiguration in a disconnected network environment K Aisopos, A DeOrio, LS Peh, V Bertacco 2011 International conference on parallel architectures and compilation …, 2011 | 127 | 2011 |
| GPU computing gems emerald edition WH Wen-Mei Elsevier, 2011 | 121* | 2011 |
| High-performance gate-level simulation with GP-GPUs D Chatterjee, A DeOrio, V Bertacco GPU Computing Gems Emerald Edition, 343-364, 2011 | 99 | 2011 |
| Dacota: Post-silicon validation of the memory subsystem in multi-core designs A DeOrio, I Wagner, V Bertacco 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 71 | 2009 |
| Machine learning-based anomaly detection for post-silicon bug diagnosis A DeOrio, Q Li, M Burgess, V Bertacco 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 491-496, 2013 | 65 | 2013 |
| Comprehensive online defect diagnosis in on-chip networks A Ghofrani, R Parikh, S Shamshiri, A DeOrio, KT Cheng, V Bertacco 2012 IEEE 30th VLSI Test Symposium (VTS), 44-49, 2012 | 58 | 2012 |
| Post-silicon verification for cache coherence A DeOrio, A Bauserman, V Bertacco 2008 IEEE International Conference on Computer Design, 348-355, 2008 | 46 | 2008 |
| Post-silicon bug diagnosis with inconsistent executions A DeOrio, DS Khudia, V Bertacco 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 755-761, 2011 | 36 | 2011 |
| Long term effects of pair programming MO Smith, A Giugliano, A DeOrio IEEE Transactions on Education 61 (3), 187-194, 2017 | 32 | 2017 |
| Gate-level simulation with GPU computing D Chatterjee, A Deorio, V Bertacco ACM Transactions on Design Automation of Electronic Systems (TODAES) 16 (3 …, 2011 | 32 | 2011 |
| DRAIN: Distributed recovery architecture for inaccessible nodes in multi-core chips A DeOrio, K Aisopos, V Bertacco, LS Peh Proceedings of the 48th Design Automation Conference, 912-917, 2011 | 24 | 2011 |
| Human computing for EDA A DeOrio, V Bertacco Proceedings of the 46th annual design automation conference, 621-622, 2009 | 24 | 2009 |
| Inferno: Streamlining verification with inferred semantics A DeOrio, AB Bauserman, V Bertacco, BC Isaksen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 24 | 2009 |
| Bridging pre-and post-silicon debugging with BiPeD A DeOrio, J Li, V Bertacco Proceedings of the International Conference on Computer-Aided Design, 95-100, 2012 | 21 | 2012 |
| Functional correctness for CMP interconnects R Abdel-Khalek, R Parikh, A DeOrio, V Bertacco 2011 IEEE 29th International Conference on Computer Design (ICCD), 352-359, 2011 | 15 | 2011 |
| DREDGE: Dynamic repartitioning during dynamic graph execution A McCrabb, E Winsor, V Bertacco Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 13 | 2019 |
