| BMF-BD: Bayesian model fusion on Bernoulli distribution for efficient yield estimation of integrated circuits C Fang, F Yang, X Zeng, X Li Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 32 | 2014 |
| Improving diagnosis efficiency via machine learning Q Huang, C Fang, S Mittal, RD Blanton 2018 IEEE International Test Conference (ITC), 1-10, 2018 | 30 | 2018 |
| Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits Q Huang, C Fang, F Yang, X Zeng, X Li Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 22 | 2015 |
| Efficient bit error rate estimation for high-speed link by Bayesian model fusion C Fang, Q Huang, F Yang, X Zeng, X Li, C Gu 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 20 | 2015 |
| Towards smarter diagnosis: A learning-based diagnostic outcome previewer Q Huang, C Fang, S Mittal, RD Blanton ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (5 …, 2020 | 12 | 2020 |
| LAIDAR: Learning for accuracy and ideal diagnostic resolution Q Huang, C Fang, RDS Blanton 2020 IEEE International Test Conference (ITC), 1-10, 2020 | 10 | 2020 |
| Adaptive test pattern reordering for diagnosis using k-nearest neighbors C Fang, Q Huang, RD Blanton 2020 IEEE International Test Conference in Asia (ITC-Asia), 59-64, 2020 | 9 | 2020 |
| Improving test chip design efficiency via machine learning Z Liu, Q Huang, C Fang, RD Blanton 2019 IEEE International Test Conference (ITC), 1-10, 2019 | 9 | 2019 |
| Diagnosis outcome preview through learning C Fang, Q Huang, S Mittal, RDS Blanton 2019 IEEE 37th VLSI Test Symposium (VTS), 1-6, 2019 | 9 | 2019 |
| Efficient performance modeling via dual-prior Bayesian model fusion for analog and mixed-signal circuits Q Huang, C Fang, F Yang, X Zeng, D Zhou, X Li Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 6 | 2016 |
| Diagnosis outcome prediction on limited data via transferred random forest Q Huang, C Fang, RDS Blanton 2020 IEEE International Test Conference in Asia (ITC-Asia), 65-70, 2020 | 5 | 2020 |
| An aggregating based model order reduction method for power grids Q Huang, X Li, C Fang, F Yang, Y Su, X Zeng Integration 55, 449-454, 2016 | 5 | 2016 |
| IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design Q Huang, C Fang, Z Liu, R Ding, RDS Blanton 2019 IEEE 37th International Conference on Computer Design (ICCD), 11-19, 2019 | 2 | 2019 |
| Efficient performance modeling of analog integrated circuits via kernel density based sparse regression C Fang, Q Huang, F Yang, X Zeng, D Zhou, X Li Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 2 | 2016 |
| Efficient test chip design via smart computation C Fang, Q Huang, Z Liu, R Ding, RD Blanton ACM Transactions on Design Automation of Electronic Systems 28 (2), 1-31, 2023 | 1 | 2023 |
| Memory-efficient adaptive test pattern reordering for accurate diagnosis C Fang, Q Huang, RDS Blanton 2021 IEEE 39th VLSI Test Symposium (VTS), 1-7, 2021 | 1 | 2021 |
| High-speed link verification based on statistical inference X Zeng, C Fang, Q Huang, F Yang, D Zhou, W Cai, W Shi 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 906-909, 2016 | 1 | 2016 |
| PGMOR: An efficient model order reduction method for power grids Q Huang, X Li, C Fang, F Yang, Y Su, X Zeng 2015 14th International Conference on Computer-Aided Design and Computer …, 2015 | 1 | 2015 |
| Machine Learning in Logic Circuit Diagnosis RD Blanton, C Fang, Q Huang, S Mittal Machine Learning Support for Fault Diagnosis of System-on-Chip, 135-171, 2022 | | 2022 |
| Integrated Circuit Test Optimization for Comprehensive Defect Characterization C Fang Carnegie Mellon University, 2021 | | 2021 |
