| Design methodology for voltage-scaled clock distribution networks C Sitik, W Liu, B Taskin, E Salman IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10 …, 2016 | 34 | 2016 |
| FinFET-based low-swing clocking C Sitik, E Salman, L Filippini, SJ Yoon, B Taskin ACM Journal on Emerging Technologies in Computing Systems (JETC) 12 (2), 1-20, 2015 | 26 | 2015 |
| Enhanced level shifter for multi-voltage operation W Liu, E Salman, C Sitik, B Taskin 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1442-1445, 2015 | 17 | 2015 |
| SLECTS: Slew-driven clock tree synthesis W Liu, C Sitik, E Salman, B Taskin, S Sundareswaran, B Huang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (4), 864-874, 2019 | 16 | 2019 |
| Timing characterization of clock buffers for clock tree synthesis C Sitik, S Lerner, B Taskin 2014 IEEE 32nd International Conference on Computer Design (ICCD), 230-236, 2014 | 15 | 2014 |
| High performance low swing clock tree synthesis with custom D flip-flop design C Sitik, L Filippini, E Salman, B Taskin 2014 IEEE Computer Society Annual Symposium on VLSI, 498-503, 2014 | 13 | 2014 |
| Skew-bounded low swing clock tree optimization C Sitik, B Taskin Proceedings of the 23rd ACM international conference on Great lakes …, 2013 | 13 | 2013 |
| A novel static D-flip-flop topology for low swing clocking M Rathore, W Liu, E Salman, C Sitik, B Taskin Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 301-306, 2015 | 9 | 2015 |
| Clock skew scheduling in the presence of heavily gated clock networks W Liu, E Salman, C Sitik, B Taskin Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 283-288, 2015 | 9 | 2015 |
| Multi-voltage domain clock mesh design C Sitik, B Taskin 2012 IEEE 30th International Conference on Computer Design (ICCD), 201-206, 2012 | 9 | 2012 |
| Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits B Taskin, AC Sitik US Patent 9,773,079, 2017 | 8 | 2017 |
| Multi-corner multi-voltage domain clock mesh design C Sitik, B Taskin Proceedings of the 23rd ACM international conference on Great lakes …, 2013 | 5 | 2013 |
| Exploiting useful skew in gated low voltage clock trees W Liu, E Salman, C Sitik, B Taskin 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2595-2598, 2016 | 4 | 2016 |
| A microcontroller-based embedded system design course with PSoC3 C Sitik, P Nagvajara, B Taskin 2013 IEEE International Conference on Microelectronic Systems Education (MSE …, 2013 | 4 | 2013 |
| Slew-driven clock tree synthesis WC Liu, E Salman, AC Sitik, B Taskin US Patent 10,338,633, 2019 | 3 | 2019 |
| Iterative skew minimization for low swing clocks C Sitik, B Taskin Integration 47 (3), 356-364, 2014 | 3 | 2014 |
| Low voltage clock tree synthesis with local gate clusters C Sitik, W Liu, B Taskin, E Salman Proceedings of the 2019 Great Lakes Symposium on VLSI, 99-104, 2019 | 2 | 2019 |
| Circuits and algorithms to facilitate low swing clocking in nanoscale technologies W Liu, E Salman, C Sitik, B Taskin, S Sundareswaran, B Huang Proceedings of the Semiconductor Research Corporation (SRC) TECHCON, 2015 | 2 | 2015 |
| Technologies for node-degree based clustering of data sets AC Sitik, A More US Patent 10,452,717, 2019 | | 2019 |
| Design and automation of voltage-scaled clock networks AC Sitik Drexel University, 2015 | | 2015 |
Baris TaskinProfessor of ECE, Drexel University在 coe.drexel.edu 的电子邮件经过验证
