| A GPGPU compiler for memory optimization and parallelism management Y Yang, P Xiang, J Kong, H Zhou ACM Sigplan Notices 45 (6), 86-97, 2010 | 410 | 2010 |
| Adaptive mode control: A static-power-efficient cache design H Zhou, MC Toburen, E Rotenberg, TM Conte ACM Transactions on Embedded Computing Systems (TECS) 2 (3), 347-372, 2003 | 253 | 2003 |
| yaSpMV: Yet another SpMV framework on GPUs S Yan, C Li, Y Zhang, H Zhou Acm Sigplan Notices 49 (8), 107-118, 2014 | 179 | 2014 |
| Understanding software approaches for GPGPU reliability M Dimitrov, M Mantor, H Zhou Proceedings of 2nd Workshop on General Purpose Processing on Graphics …, 2009 | 162 | 2009 |
| Hardware-software integrated approaches to defend against software cache-based side channel attacks J Kong, O Aciiçmez, JP Seifert, H Zhou 2009 IEEE 15th international symposium on high performance computer …, 2009 | 152 | 2009 |
| Locality-driven dynamic GPU cache bypassing C Li, SL Song, H Dai, A Sidelnik, SKS Hari, H Zhou Proceedings of the 29th ACM on International Conference on Supercomputing, 67-77, 2015 | 139 | 2015 |
| Optimizing memory efficiency for deep convolutional neural networks on GPUs C Li, Y Yang, M Feng, S Chakradhar, H Zhou SC'16: Proceedings of the International Conference for High Performance …, 2016 | 138 | 2016 |
| Dual-core execution: Building a highly scalable single-thread instruction window H Zhou 14th International Conference on Parallel Architectures and Compilation …, 2005 | 135 | 2005 |
| CPU-assisted GPGPU on fused CPU-GPU architectures Y Yang, P Xiang, M Mantor, H Zhou IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012 | 133 | 2012 |
| Deconstructing new cache designs for thwarting software cache-based side channel attacks J Kong, O Aciicmez, JP Seifert, H Zhou Proceedings of the 2nd ACM workshop on Computer security architectures, 25-34, 2008 | 130 | 2008 |
| Effisha: A software framework for enabling effficient preemptive scheduling of gpu G Chen, Y Zhao, X Shen, H Zhou Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of …, 2017 | 108 | 2017 |
| CUDA-NP: Realizing nested thread-level parallelism in GPGPU applications Y Yang, H Zhou ACM SIGPLAN Notices 49 (8), 93-106, 2014 | 91 | 2014 |
| Improving privacy and lifetime of PCM-based main memory J Kong, H Zhou 2010 IEEE/IFIP International Conference on Dependable Systems & Networks …, 2010 | 90 | 2010 |
| Warp-level divergence in GPUs: Characterization, impact, and mitigation P Xiang, Y Yang, H Zhou 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 88 | 2014 |
| Enhancing memory level parallelism via recovery-free value prediction H Zhou, TM Conte Proceedings of the 17th annual International Conference on Supercomputing …, 2003 | 88 | 2003 |
| Improving software security via runtime instruction-level taint checking J Kong, CC Zou, H Zhou Proceedings of the 1st workshop on Architectural and system support for …, 2006 | 73 | 2006 |
| Quantum circuits for dynamic runtime assertions in quantum computation J Liu, GT Byrd, H Zhou Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 71 | 2020 |
| Shared memory multiplexing: A novel way to improve GPGPU throughput Y Yang, P Xiang, M Mantor, N Rubin, H Zhou Proceedings of the 21st international conference on Parallel architectures …, 2012 | 66 | 2012 |
| Detecting global stride locality in value streams H Zhou, J Flanagan, TM Conte Proceedings of the 30th annual international symposium on Computer …, 2003 | 65 | 2003 |
| Adaptive cache bypassing for inclusive last level caches S Gupta, H Gao, H Zhou 2013 IEEE 27th International Symposium on Parallel and Distributed …, 2013 | 59 | 2013 |
Yi YangNEC Labs在 nec-labs.com 的电子邮件经过验证
