| A high-performance droplet routing algorithm for digital microfluidic biochips M Cho, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 205* | 2008 |
| BoxRouter: A new global router based on box expansion and progressive ILP M Cho, DZ Pan Proceedings of the 43rd annual Design Automation Conference, 373-378, 2006 | 170 | 2006 |
| BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router M Cho, K Lu, K Yuan, DZ Pan 2007 IEEE/ACM International Conference on Computer-Aided Design, 503-508, 2007 | 142 | 2007 |
| MEC: Memory-efficient convolution for deep neural network M Cho, D Brand International Conference on Machine Learning, 815-824, 2017 | 138 | 2017 |
| Blueconnect: Decomposing all-reduce for deep learning on heterogeneous network hierarchy M Cho, U Finkler, D Kung, H Hunter Proceedings of Machine Learning and Systems 1, 241-251, 2019 | 109 | 2019 |
| TACO: Temperature aware clock-tree optimization M Cho, S Ahmedtt, DZ Pan ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 107 | 2005 |
| Double patterning technology friendly detailed routing M Cho, Y Ban, DZ Pan 2008 IEEE/ACM International Conference on Computer-Aided Design, 506-511, 2008 | 97 | 2008 |
| Wire density driven global routing for CMP variation and timing M Cho, DZ Pan, H Xiang, R Puri Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 94 | 2006 |
| Relative ordering circuit synthesis M Cho, R Puri, H Ren, X Tang, H Xiang, MM Ziegler US Patent 8,756,541, 2014 | 83 | 2014 |
| A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography JS Yang, K Lu, M Cho, K Yuan, DZ Pan 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 637-644, 2010 | 83 | 2010 |
| Powerai ddl M Cho, U Finkler, S Kumar, D Kung, V Saxena, D Sreedhar arXiv preprint arXiv:1708.02188, 2017 | 76 | 2017 |
| Enabling real-time multi-messenger astrophysics discoveries with deep learning EA Huerta, G Allen, I Andreoni, JM Antelis, E Bachelet, GB Berriman, ... Nature Reviews Physics 1 (10), 600-608, 2019 | 75 | 2019 |
| BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability M Cho, K Lu, K Yuan, DZ Pan ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (2 …, 2009 | 69 | 2009 |
| Optimal layout decomposition for double patterning technology X Tang, M Cho 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 9-13, 2011 | 55 | 2011 |
| PARADIS: An efficient parallel algorithm for in-place radix sort M Cho, D Brand, R Bordawekar, U Finkler, V Kulandaisamy, R Puri Proceedings of the VLDB Endowment 8 (12), 1518-1529, 2015 | 54 | 2015 |
| Converged large block and structured synthesis for high performance microprocessor designs M Cho, VN Kravets, S Krishnaswamy, D Kucar, J Narasimhan, R Puri, ... US Patent 8,271,920, 2012 | 52 | 2012 |
| History-based VLSI legalization using network flow M Cho, H Ren, H Xiang, R Puri Proceedings of the 47th Design Automation Conference, 286-291, 2010 | 43 | 2010 |
| Blueconnect: Novel hierarchical all-reduce on multi-tired network for deep learning M Cho, U Finkler, D Kung Proceedings of the 2nd SysML Conference, 2019 | 39 | 2019 |
| ELIAD: Efficient lithography aware detailed router with compact post-OPC printability prediction M Cho, K Yuan, Y Ban, DZ Pan Proceedings of the 45th annual Design Automation Conference, 504-509, 2008 | 38 | 2008 |
| Llm in a flash: Efficient large language model inference with limited memory K Alizadeh, I Mirzadeh, D Belenko, K Khatamifard, M Cho, CC Del Mundo, ... arXiv preprint arXiv:2312.11514, 2023 | 35 | 2023 |
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at Austin在 ece.utexas.edu 的电子邮件经过验证
