| Finfet transistor circuit ST Becker, MC Smayling, D Gandhi, J Mali, C Lambert, JR Quandt, D Fox US Patent 8,863,063, 2014 | 171 | 2014 |
| Enforcement of semiconductor structure regularity for localized transistors and interconnect S Kornachuk, J Mali, C Lambert, ST Becker US Patent 8,453,094, 2013 | 117 | 2013 |
| Optimizing layout of irregular structures in regular layout context S Kornachuk, C Lambert, J Mali, B Reed, ST Becker US Patent 8,448,102, 2013 | 109 | 2013 |
| Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes ST Becker, J Mali, C Lambert US Patent 8,395,224, 2013 | 107 | 2013 |
| Enforcement of semiconductor structure regularity for localized transistors and interconnect S Kornachuk, J Mali, C Lambert, ST Becker US Patent 8,701,071, 2014 | 89 | 2014 |
| Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts ST Becker, J Mali, C Lambert US Patent 8,847,329, 2014 | 87 | 2014 |
| Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track ST Becker, J Mali, C Lambert US Patent 8,836,045, 2014 | 87 | 2014 |
| Circuits with linear finfet structures ST Becker, MC Smayling, D Gandhi, J Mali, C Lambert, JR Quandt, D Fox US Patent 9,009,641, 2015 | 86 | 2015 |
| Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track ST Becker, J Mali, C Lambert US Patent 8,735,995, 2014 | 83 | 2014 |
| Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides … ST Becker, J Mali, C Lambert US Patent 8,405,163, 2013 | 83 | 2013 |
| Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features … ST Becker, J Mali, C Lambert US Patent 8,575,706, 2013 | 75 | 2013 |
| Enforcement of semiconductor structure regularity for localized transistors and interconnect S Kornachuk, J Mali, C Lambert, ST Becker US Patent 9,202,779, 2015 | 58 | 2015 |
| Enforcement of semiconductor structure regularity for localized transistors and interconnect S Kornachuk, J Mali, C Lambert, ST Becker US Patent 9,530,734, 2016 | 28 | 2016 |
| Dual port memory core cell architecture with matched bit line capacitances J Mali, B Hold US Patent 7,002,258, 2006 | 21 | 2006 |
| Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically … ST Becker, J Mali, C Lambert US Patent 8,866,197, 2014 | 16 | 2014 |
| Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels ST Becker, J Mali, C Lambert US Patent 8,729,606, 2014 | 15 | 2014 |
| Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending … ST Becker, J Mali, C Lambert US Patent 8,569,841, 2013 | 15 | 2013 |
| Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same ST Becker, J Mali, C Lambert US Patent 9,536,899, 2017 | 14 | 2017 |
| Integrated circuit within semiconductor chip including cross-coupled transistor configuration ST Becker, J Mali, C Lambert US Patent 8,853,794, 2014 | 13 | 2014 |
| Method and apparatus for eliminating bitline voltage offsets in memory devices JC Mali, ST Becker US Patent 6,016,390, 2000 | 13 | 2000 |
