| Defect level evaluation in an IC design environment JT De Sousa, FM Gonçalves, JP Teixeira, C Marzocca, F Corsi, ... IEEE transactions on computer-aided design of integrated circuits and …, 1996 | 72 | 1996 |
| A SAT Solver using Reconfigurable Hardware and Virtual Logic M Abramovici, J.T. de Sousa SAT 2000, Highlights of Satisfiability Research in the Year 2000,, 377-402, 2001 | 53 | 2001 |
| A SAT solver using reconfigurable hardware and virtual logic M Abramovici, JT De Sousa Journal of Automated Reasoning 24 (1-2), 5-36, 2000 | 53 | 2000 |
| IC Defects-Based Testability Analysis JJT Sousa, FM Gonçalves, ... International Test Conference (ITC), 500-509, 1991 | 50 | 1991 |
| Moving deep learning to the edge MP Véstias, RP Duarte, JT de Sousa, HC Neto Algorithms 13 (5), 125, 2020 | 48 | 2020 |
| A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware M Abramovici, JT de Sousa, D Saab Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 684-690, 1999 | 48 | 1999 |
| Network core access architecture JT De Sousa, NCC Lourenco, NGDR Ribeiro, VMG Martins, RJS Martins US Patent 8,019,832, 2011 | 47 | 2011 |
| A configurable hardware/software approach to SAT solving JT de Sousa, JM Da Silva, M Abramovici The 9th Annual IEEE Symposium on Field-Programmable Custom Computing …, 2001 | 44 | 2001 |
| Virtual logic system for solving satisfiability problems using reconfigurable hardware M Abramovici, JT De Sousa US Patent 6,442,732, 2002 | 43 | 2002 |
| Reducing the complexity of defect level modeling using the clustering effect JT de Sousa, VD Agrawal Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2000 | 35 | 2000 |
| Parallel backtracing for satisfiability on reconfigurable hardware M Abramovici, JT De Sousa, DG Saab US Patent 6,292,916, 2001 | 34 | 2001 |
| A 1.7-mW -92-dBm Sensitivity Low-IF Receiver in 0.13-μm CMOS for Bluetooth LE Applications. M Pereira, J T. de Sousa, J Freire, J Vaz IEEE Transactions on Microwave Theory and Techniques, 1-15, 2018 | 32* | 2018 |
| A Full Featured Configurable Accelerator for Object Detection with YOLO D Pestana, PR Miranda, JD Lopes, RP Duarte, M Véstias, H C. Neto, ... IEEE Access, 2021 | 31 | 2021 |
| Physical DFT for High Coverage of Realistic Faults M Saraiva, P Casimiro, M Santos, JT Sousa, FM Gonçalves, I Teixeira, ... Int. Test Conference (ITC), 642-651, 1992 | 28 | 1992 |
| Parallel Dot-Products for Deep Learning on FPGA M Véstias, R Duarte, JT de Sousa, H Neto 27th Int. Conference on Field Programmable Logic and Applications, 2017 | 27 | 2017 |
| Fault Modeling and Defect Level Projections in Digital ICs JT Sousa, FM Gonçalves, JP Teixeira, TW Williams European Design and Test Conference (ED&TC), 436-442, 1994 | 24 | 1994 |
| On implementing a configware/software SAT solver NA Reis, JT de Sousa Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom …, 2002 | 21 | 2002 |
| A fast and scalable architecture to run convolutional neural networks in low density FPGAs MP Véstias, RP Duarte, JT de Sousa, HC Neto Microprocessors and Microsystems 77, 103136, 2020 | 20 | 2020 |
| Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs HN Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa 28th International Conference on Field Programmable Logic and Applications (FPL), 2018 | 20 | 2018 |
| Physical design of testable CMOS digital integrated circuits JJHT de Sousa, FM Goncalves, JP Teixeira IEEE Journal of Solid State Circuits 26 (7), 1064-1072, 1991 | 20 | 1991 |
Mário Véstiasinesc-id在 deetc.isel.ipl.pt 的电子邮件经过验证
