| Proof of concept of home IoT connected vehicles Y Kim, H Oh, S Kang Sensors 17 (6), 1289, 2017 | 36 | 2017 |
| A scalable and parallel test access strategy for NoC-based multicore system T Han, I Choi, H Oh, S Kang 2014 IEEE 23rd Asian Test Symposium, 81-86, 2014 | 16 | 2014 |
| An on-chip error detection method to reduce the post-silicon debug time H Oh, T Han, I Choi, S Kang IEEE Transactions on Computers 66 (1), 38-44, 2016 | 12 | 2016 |
| DRAM-based error detection method to reduce the post-silicon debug time for multiple identical cores H Oh, I Choi, S Kang IEEE Transactions on Computers 66 (9), 1504-1517, 2017 | 8 | 2017 |
| On-chip error detection reusing built-in self-repair for silicon debug H Lee, H Oh, S Kang IEEE Access 9, 56443-56456, 2021 | 6 | 2021 |
| A new scan chain reordering method for low power consumption based on care bit density K Cho, J Kim, H Oh, S Lee, S Kang 2019 International SoC Design Conference (ISOCC), 134-135, 2019 | 6 | 2019 |
| A 2-D compaction method using macro block for post-silicon validation W Jung, H Oh, D Kang, S Kang 2015 International SoC Design Conference (ISOCC), 41-42, 2015 | 5 | 2015 |
| Low Power Scan Chain Architecture Based on Circuit Topology H Kim, H Oh, S Lee, S Kang 2018 International SoC Design Conference (ISOCC), 267-268, 2018 | 4 | 2018 |
| Test resource reused debug scheme to reduce the post-silicon debug cost I Choi, H Oh, YW Lee, S Kang IEEE Transactions on Computers 67 (12), 1835-1839, 2018 | 4 | 2018 |
| Parallelized network-on-chip-reused test access mechanism for multiple identical cores T Han, I Choi, H Oh, S Kang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 3 | 2015 |
| A debug scheme to improve the error identification in post-silicon validation I Choi, W Jung, H Oh, S Kang PloS one 13 (9), e0202216, 2018 | 2 | 2018 |
| Thermal aware test scheduling for NTV circuit J Lim, H Oh, H Kim, S Kang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 2 | 2017 |
| Reconfigurable scan architecture for test power and data volume reduction H Oh, H Kim, J Lim, S Kang ieice electronics express 14 (13), 20170415-20170415, 2017 | 2 | 2017 |
| Process variation-aware bridge fault analysis H Kim, I Choi, J Lim, H Oh, S Kang 2016 International SoC Design Conference (ISOCC), 147-148, 2016 | 2 | 2016 |
| A novel X-filling method for capture power reduction H Kim, H Oh, J Lim, S Kang ieice electronics express 14 (23), 20171093-20171093, 2017 | 1 | 2017 |
| A new online test and debug methodology for automotive camera image processing system H Oh, I Choi, S Kang 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 370-371, 2016 | 1 | 2016 |
| An online test and debug methodology for automotive image processing system H Oh, I Choi, T Han, W Jung, B Moon, S Kang 2014 International SoC Design Conference (ISOCC), 226-227, 2014 | 1 | 2014 |
| Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test H Oh, H Kim, S Lee, S Kang 2018 International SoC Design Conference (ISOCC), 7-8, 2018 | | 2018 |
| A selective error data capture method using on-chip DRAM for silicon debug of multi-core design H Oh, H Kim, J Lim, S Kang 2017 International SoC Design Conference (ISOCC), 121-122, 2017 | | 2017 |
| Dynamic voltage frequency scaling‐aware refresh management for 3D DRAM over processor architecture J Lim, H Kim, H Oh, S Kang Electronics Letters 53 (14), 910-912, 2017 | | 2017 |
sungho kangYonsei University Professor at the School of Electrical and Electronic Engineering在 soc.yonsei.ac.kr 的电子邮件经过验证
sungho kangYonsei University Professor at the School of Electrical and Electronic Engineering在 soc.yonsei.ac.kr 的电子邮件经过验证