| A 20k-spin Ising chip to solve combinatorial optimization problems with CMOS annealing M Yamaoka, C Yoshimura, M Hayashi, T Okuyama, H Aoki, H Mizuno IEEE Journal of Solid-State Circuits 51 (1), 303-309, 2015 | 423 | 2015 |
| 24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing M Yamaoka, C Yoshimura, M Hayashi, T Okuyama, H Aoki, H Mizuno 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 125 | 2015 |
| Semiconductor device M Hayashi, C Yoshimura, M Yamaoka US Patent 10,037,391, 2018 | 122* | 2018 |
| 2.6 A 2× 30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems T Takemoto, M Hayashi, C Yoshimura, M Yamaoka 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 52-54, 2019 | 89 | 2019 |
| Semiconductor device capable of attaining ground state in an ising model C Yoshimura, M Yamaoka, T Sekiguchi, T Tomaru US Patent 9,633,715, 2017 | 73 | 2017 |
| A 2 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization … T Takemoto, M Hayashi, C Yoshimura, M Yamaoka IEEE Journal of Solid-State Circuits 55 (1), 145-156, 2019 | 60 | 2019 |
| 4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems T Takemoto, K Yamamoto, C Yoshimura, M Hayashi, M Tada, H Saito, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 64-66, 2021 | 55 | 2021 |
| Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing C Yoshimura, M Hayashi, T Okuyama, M Yamaoka International Journal of Networking and Computing 7 (2), 154-172, 2017 | 52 | 2017 |
| Uncertain behaviours of integrated circuits improve computational performance C Yoshimura, M Yamaoka, M Hayashi, T Okuyama, H Aoki, ... Scientific reports 5, 16213, 2015 | 44 | 2015 |
| Fpga-based annealing processor for ising model C Yoshimura, M Hayashi, T Okuyama, M Yamaoka 2016 Fourth International Symposium on Computing and Networking (CANDAR …, 2016 | 41 | 2016 |
| Spatial computing architecture using randomness of memory cell stability under voltage control C Yoshimura, M Yamaoka, H Aoki, H Mizuno 2013 European Conference on Circuit Theory and Design (ECCTD), 1-4, 2013 | 38 | 2013 |
| Accelerator chip for ground-state searches of ising model with asynchronous random pulse distribution M Hayashi, M Yamaoka, C Yoshimura, T Okuyama, H Aoki, H Mizuno International Journal of Networking and Computing 6 (2), 195-211, 2016 | 30 | 2016 |
| An accelerator chip for ground-state searches of the Ising model with asynchronous random pulse distribution M Hayashi, M Yamaoka, C Yoshimura, T Okuyama, H Aoki, H Mizuno 2015 Third International Symposium on Computing and Networking (CANDAR), 542-546, 2015 | 30 | 2015 |
| CMOS annealing machine: A domain-specific architecture for combinatorial optimization problem C Yoshimura, M Hayashi, T Takemoto, M Yamaoka 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 673-678, 2020 | 25 | 2020 |
| Semiconductor device C Yoshimura, M Yamaoka, M Hayashi US Patent 9,331,695, 2016 | 24 | 2016 |
| Computing architecture to perform approximated simulated annealing for Ising models T Okuyama, C Yoshimura, M Hayashi, M Yamaoka 2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2016 | 23 | 2016 |
| Information processing apparatus and information processing method C Yoshimura, M Yamaoka, K Kawarabayashi, T Fukunaga, T Takaguchi, ... US Patent 10,089,421, 2018 | 22* | 2018 |
| Ising Computer M Yamaoka, C Yoshimura, M Hayashi, T Okuyama, H Aoki, H Mizuno Hitachi Review 65 (6), 157, 2016 | 22 | 2016 |
| CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems M Yamaoka, T Okuyama, M Hayashi, C Yoshimura, T Takemoto 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2019 | 21 | 2019 |
| Data transfer unit for computer C Yoshimura, Y Nagasaka, N Sukegawa, K Takayama US Patent App. 12/546,386, 2010 | 19 | 2010 |
