| The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ... IEEE Micro 38 (2), 30-41, 2018 | 122 | 2018 |
| A new approach to automatic memory banking using trace-based address mining Y Zhou, KM Al-Hawaj, Z Zhang Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 41 | 2017 |
| Celerity: An open source RISC-V tiered accelerator fabric T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ... Symp. on High Performance Chips (Hot Chips), 2017 | 35 | 2017 |
| A 1.4 GHz 695 Giga Risc-V inst/s 496-core manycore processor with mesh on-chip network and an all-digital synthesized PLL in 16nm CMOS A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ... 2019 Symposium on VLSI Circuits, C30-C31, 2019 | 27 | 2019 |
| Evaluating celerity: A 16-nm 695 Giga-RISC-V instructions/s manycore processor with synthesizable PLL A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ... IEEE Solid-State Circuits Letters 2 (12), 289-292, 2019 | 26 | 2019 |
| Towards a reconfigurable bit-serial/bit-parallel vector accelerator using in-situ processing-in-sram K Al-Hawaj, O Afuye, S Agwa, A Apsel, C Batten 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 20 | 2020 |
| CAPE: A Content-Addressable Processing Engine H Caminal, K Yang, S Srinivasa, AK Ramanathan, K Al-Hawaj, T Wu, ... 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 19 | 2021 |
| Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs J Kim, S Jiang, C Torng, M Wang, S Srinath, B Ilbeyi, K Al-Hawaj, C Batten Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 14 | 2017 |
| Experiences using the risc-v ecosystem to design an accelerator-centric soc in tsmc 16nm TAKAH Aporva, ASDS Davidson, PGGLA Rao, ARNSC Torng, LVBVS Xie, ... 1st Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017 | 14 | 2017 |
| A New Era of Silicon Prototyping in Computer Architecture Research C Torng, S Jiang, K Al-Hawaj, I Bukreyev, B Ilbeyi, T Ta, L Cheng, ... The RISC-V Day Workshop at the 51st Int’l Symp. on Microarchitecture, 2018 | 4 | 2018 |
| Content-addressable processing engine JF Martínez, H Caminal, K Yang, K Al-Hawaj, C Batten US Patent 11,461,097, 2022 | 3 | 2022 |
| big. VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip T Ta, K Al-Hawaj, N Cebry, Y Ou, E Hall, C Golden, C Batten 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 181-198, 2022 | 3 | 2022 |
| Celerity: An open source RISC-V tiered accelerator fabric S Davidson, K Al-Hawaj, A Rovinski Hot Chips: A Symposium on High Performance Chips (HC29, 2017 | 2 | 2017 |
| EVE: Ephemeral Vector Engines K Al-Hawaj, T Ta, N Cebry, S Agwa, O Afuye, E Hall, C Golden, AB Apsel, ... 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 1 | 2023 |
| Unified Cache: A Case for Low-Latency Communication K Al-Hawaj, S Campanoni, GY Wei, D Brooks 3rd International Workshop on Parallelism in Mobile Platforms (PRISM …, 2015 | 1 | 2015 |
| Content-addressable processing engine JF Martínez, H Caminal, K Yang, K Al-Hawaj, C Batten US Patent 12,001,841, 2024 | | 2024 |
| Ephemeral Vector Engines K Al-Hawaj Cornell University, 2022 | | 2022 |
Christopher BattenCornell University在 cornell.edu 的电子邮件经过验证
