| A-106dBm 33nW bit-level duty-cycled tuned RF wake-up receiver J Moody, A Dissanayake, H Bishop, R Lu, N Liu, D Duvvuri, A Gao, ... 2019 symposium on VLSI Circuits, C86-C87, 2019 | 26 | 2019 |
| 30.1 A temperature-robust 27.6 nW− 65dBm wakeup receiver at 9.6 GHz X-band P Bassirian, D Duvvuri, DS Truesdell, N Liu, BH Calhoun, SM Bowers 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 460-462, 2020 | 19 | 2020 |
| Design of an S-band nanowatt-level wakeup receiver with envelope detector-first architecture P Bassirian, D Duvvuri, N Liu, D Truesdell, HY Tsao, NS Barker, ... IEEE Transactions on Microwave Theory and Techniques 68 (9), 3920-3929, 2020 | 17 | 2020 |
| A highly reconfigurable bit-level duty-cycled TRF receiver achieving− 106-dBm sensitivity and 33-nW average power consumption J Moody, A Dissanayake, H Bishop, R Lu, N Liu, D Duvvuri, A Gao, ... IEEE Solid-State Circuits Letters 2 (12), 309-312, 2019 | 15 | 2019 |
| A 184-nW,− 78.3-dBm sensitivity antenna-coupled supply, temperature, and interference-robust wake-up receiver at 4.9 GHz X Shen, D Duvvuri, P Bassirian, HL Bishop, X Liu, A Dissanayake, ... IEEE Transactions on Microwave Theory and Techniques 70 (1), 744-757, 2021 | 12 | 2021 |
| A new hybrid circuit topology for simultaneous bidirectional signaling over on-chip interconnects D Duvvuri, S Agarwal, VSR Pasupureddi 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2342-2345, 2016 | 9 | 2016 |
| An integrated common gate CTLE receiver front end with charge mode adaptation D Duvvuri, VSR Pasupureddi 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 12-17, 2016 | 7 | 2016 |
| A 366 nW,− 74.5 dBm sensitivity antenna-coupled wakeup receiver at 4.9 GHz with integrated voltage regulation and references D Duvvuri, X Shen, P Bassirian, HL Bishop, X Liu, CH Chen, ... 2021 IEEE MTT-S International Microwave Symposium (IMS), 641-645, 2021 | 2 | 2021 |
| 100-Mbps transceiver for enhanced MIL-STD-1553 D Duvvuri, PVS Rao, J Chattopadhyay 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 316-319, 2014 | 2 | 2014 |
| A-102dBm Sensitivity, 2.2 μA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving-30dB SIR L Zhang, D Duvvuri, S Bhattacharya, A Dissanayake, X Liu, HL Bishop, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 1 | 2023 |
| Design and analysis of a current mode integrated CTLE with charge mode adaptation D Duvvuri, VSR Pasupureddi Microelectronics Journal 53, 81-89, 2016 | 1 | 2016 |
| A-102 dBm Sensitivity Multi-Channel Heterodyne Wake-Up Receiver With Integrated ADPLL L Zhang, D Duvvuri, S Bhattacharya, A Dissanayake, X Liu, HL Bishop, ... IEEE Open Journal of the Solid-State Circuits Society, 2024 | | 2024 |
Steven M. BowersAssociate Professor of Electrical and Computer Engineering, University of Virginia在 virginia.edu 的电子邮件经过验证
