| A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive CTLE and DFE using biased data-level reference J Lee, K Lee, H Kim, B Kim, K Park, DK Jeong IEEE Journal of Solid-State Circuits 55 (8), 2186-2195, 2020 | 53 | 2020 |
| A 192-Gb 12-high 896-GB/s HBM3 DRAM with a TSV auto-calibration scheme and machine-learning-based layout optimization MJ Park, J Lee, K Cho, J Park, J Moon, SH Lee, TK Kim, S Oh, S Choi, ... IEEE Journal of Solid-State Circuits 58 (1), 256-269, 2022 | 40 | 2022 |
| A 6.7–11.2 Gb/s, 2.25 pJ/bit, single-loop referenceless CDR with multi-phase, oversampling PFD in 65-nm CMOS K Park, W Bae, J Lee, J Hwang, DK Jeong IEEE Journal of Solid-State Circuits 53 (10), 2982-2993, 2018 | 39 | 2018 |
| A 0.1-pJ/b/dB 28-Gb/s maximum-eye tracking, weight-adjusting MM CDR and adaptive DFE with single shared error sampler MC Choi, HG Ko, J Oh, HY Joo, K Lee, DK Jeong 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 36 | 2020 |
| 29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and −65dBc reference spur using time-division dual calibration S Kim, HG Ko, SY Cho, J Lee, S Shin, MS Choo, H Chi, DK Jeong 2017 IEEE International Solid-State Circuits Conference (ISSCC), 494-495, 2017 | 34 | 2017 |
| A 4–20-Gb/s 1.87-pJ/b continuous-rate digital CDR circuit with unlimited frequency acquisition capability in 65-nm CMOS K Park, K Lee, SY Cho, J Lee, J Hwang, MS Choo, DK Jeong IEEE Journal of Solid-State Circuits 56 (5), 1597-1607, 2020 | 30 | 2020 |
| A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection SY Cho, S Kim, MS Choo, J Lee, HG Ko, S Jang, SH Chu, W Bae, Y Kim, ... ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015 | 25 | 2015 |
| A 2.44-pJ/b 1.62–10-Gb/s receiver for next generation video interface equalizing 23-dB loss with adaptive 2-tap data DFE and 1-tap edge DFE J Lee, K Park, K Lee, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 65 (10), 1295-1299, 2018 | 22 | 2018 |
| A 0.1 pJ/b/dB 1.62-to-10.8 Gb/s video interface receiver with fully adaptive equalization using un-even data level J Lee, K Lee, H Kim, B Kim, K Park, DK Jeong 2019 Symposium on VLSI Circuits, C198-C199, 2019 | 14 | 2019 |
| An adaptive offset cancellation scheme and shared-summer adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s low-power receiver in 40 nm CMOS K Lee, H Kim, W Jung, J Lee, H Ju, K Park, O Kim, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 68 (2), 622-626, 2020 | 10 | 2020 |
| A 4-to-20Gb/s 1.87 pJ/b referenceless digital CDR with unlimited frequency detection capability in 65nm CMOS K Park, K Lee, SY Cho, J Lee, J Hwang, MS Choo, DK Jeong 2019 Symposium on VLSI Circuits, C194-C195, 2019 | 9 | 2019 |
| A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS K Park, W Bae, H Ju, J Lee, GS Jeong, Y Kim, DK Jeong 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2389-2392, 2015 | 9 | 2015 |
| A maximum-eye-tracking CDR with biased data-level and eye slope detector for near-optimal timing adaptation HY Joo, J Lee, H Ju, HG Ko, JM Yoon, B Kang, DK Jeong IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (12 …, 2020 | 8 | 2020 |
| A 2.5–32 Gb/s gen 5-PCIe receiver with multi-rate CDR engine and hybrid DFE MC Choi, S Lee, S Roh, K Lee, J Oh, S Kim, K Kim, WS Choi, J Kim, ... IEEE Transactions on Circuits and Systems II: Express Briefs 69 (6), 2677-2681, 2022 | 7 | 2022 |
| A 55.1 mW 1.62-to-8.1 Gb/s video interface receiver generating up to 680 MHz stream clock over 20 dB loss channel K Park, J Lee, K Lee, MS Choo, S Jang, SH Chu, S Kim, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 64 (12), 1432-1436, 2017 | 7 | 2017 |
| A PVT variation-robust all-digital injection-locked clock multiplier with real-time offset tracking using time-division dual calibration MS Choo, S Kim, HG Ko, SY Cho, K Park, J Lee, S Shin, H Chi, DK Jeong IEEE Journal of Solid-State Circuits 56 (8), 2525-2538, 2021 | 6 | 2021 |
| A 48 Gb/s PAM-4 receiver with pre-cursor adjustable baud-rate phase detector in 40 nm CMOS W Jung, K Lee, K Park, H Ju, J Lee, DK Jeong IEEE Journal of Solid-State Circuits 58 (5), 1414-1424, 2022 | 5 | 2022 |
| A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS K Lee, W Jung, H Ju, J Lee, DK Jeong 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021 | 5 | 2021 |
| A 48Gb/S 2.4 pJ/B PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS H Ju, K Lee, W Jung, DK Jeong 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021 | 5 | 2021 |
| A 8.4 Gb/s low power transmitter with 1.66 pJ/b using 40: 1 Serializer for displayport interface W Jung, J Lee, K Lee, H Kim, DK Jeong 2020 International SoC Design Conference (ISOCC), 41-42, 2020 | 5 | 2020 |
