| A 7 bit, 3.75 ps resolution two-step time-to-digital converter in 65 nm CMOS using pulse-train time amplifier KS Kim, YH Kim, WS Yu, SH Cho IEEE Journal of Solid-State Circuits 48 (4), 1009-1017, 2013 | 231 | 2013 |
| A hybrid-domain two-step time-to-digital converter using a switch-based time-to-voltage converter and SAR ADC J Kim, YH Kim, KS Kim, W Yu, SH Cho IEEE Transactions on Circuits and Systems II: Express Briefs 62 (7), 631-635, 2015 | 40 | 2015 |
| 23.1 a 7.5 Gb/s/pin LPDDR5 SDRAM with WCK clocking and non-target ODT for high speed and with DVFS, internal data copy, and deep-sleep mode for low power KS Ha, CK Lee, D Lee, D Moon, JH Jang, HR Hwang, H Chi, J Park, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 378-380, 2019 | 24 | 2019 |
| A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM with various high-speed and low-power techniques KS Ha, CK Lee, D Lee, D Moon, HR Hwang, D Park, YH Kim, YH Son, ... IEEE Journal of Solid-State Circuits 55 (1), 157-166, 2019 | 17 | 2019 |
| Time-interleaved single-slope ADC using counter-based time-to-digital converter HT Choi, YH Kim, KS Kim, J Kim, SH Cho 2011 IEEE International Symposium on Radio-Frequency Integration Technology …, 2011 | 17 | 2011 |
| A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages YH Kim, J Lee, SH Cho Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010 | 17 | 2010 |
| A 1-GS/s 9-bit zero-crossing-based pipeline ADC using a resistor as a current source YH Kim, SH Cho IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (7 …, 2016 | 14 | 2016 |
| Nonvolatile memory device and operating method of the same YH Kim, TY Oh, JH Jang, SJ Cho US Patent 10,607,660, 2020 | 5 | 2020 |
| A time-domain flash ADC immune to voltage controlled delay line non-linearity YH Kim, SH Cho 2011 9th IEEE International Conference on ASIC, 469-471, 2011 | 3 | 2011 |
| Memory device including a plurality of power rails and method of operating the same YH Kim, TY Oh, JH Jang, SJ Cho, KS Ha US Patent 10,529,407, 2020 | 2 | 2020 |
| A time-based successive approximation register analog-to-digital converter using a pulse width modulation technique with a single capacitor YH Kim, SH Cho 2009 International SoC Design Conference (ISOCC), 321-324, 2009 | 2 | 2009 |
| Memory device including dynamic voltage and frequency scaling switch and method of operating the same YH Kim, TY Oh, JH Jang, KS Ha US Patent 10,535,394, 2020 | 1 | 2020 |
| 시간다중분할 아날로그 디지털 변환기를 위한 단일 정렬 Sample-and-Hold 회로 김영화， 조성환 대한전자공학회 학술대회, 354-356, 2014 | | 2014 |
| Successive approximation analog-to-digital converter HK Yu, SH Han, YH Kim, SH Cho US Patent 8,274,420, 2012 | | 2012 |
